User's Manual

PMAC2 User Manual
92 Using the PMAC2 to Interrupt the Host Computer
Interrupt Mask Control Register (Base+10)
This register permits the PC to mask out interrupt signals that the user does not want to interrupt the PC.
Writing a 1 to a bit in this register enables the corresponding signal to interrupt the PC; writing a 0 to a bit
in this register disables (masks out) that signal. Note that this polarity is the opposite of an 8259 PIC used
on PMAC1 or in the PC. This register can be read at any time to find which signals are masked without
affecting the masking.
Interrupt Edge/Level Control Register (Base+11)
This register permits the PC to control whether an interrupt signal interrupts the PC on an edge-triggered
basis or by level. Writing a 1 to a bit in this register sets the corresponding signal for a level-triggered
interrupt; writing a 0 to a bit in this register sets that signal for an edge-triggered interrupt. Edge-
triggered interrupts are the default, and are more useful.
If an interrupt is edge-triggered, in order for that signal to generate another interrupt to the PC (after the
PC clears the interrupts by writing to Base+8), the signal must go low, then high again. If an interrupt is
level-triggered, if the signal is still high after the PC clears the interrupts, it will immediately interrupt the
PC again.
Interrupt Source Signals
In-Position
The in-position signal goes true if PMAC2 determines that all motors in the addressed coordinate system
are in position. For a motor to be in-position, the following conditions must be met: the servo loop must
be closed, the desired velocity must be zero, the move timer must be off (it must be in some kind of
indefinite wait, not in a move, dwell, or delay), and the following error magnitude must be smaller than
Ix28. These conditions must be true for (I7+1) consecutive background scans.
Buffer-Request
The buffer-request signal goes true when an open motion program buffer, particularly a rotary buffer, is
ready to accept another line from the PC. For the fixed motion program buffers (PROG), the ready state
is controlled by I18; for the rotary program buffers (ROT), the ready state is controlled by I16 and I17.
Refer to Rotary Motion Program Buffers under Writing a Motion Program for more details.
Fatal Following Error
The fatal following error signal goes true when any axis in the addressed coordinate system exceeds its
fatal following error limit as set by Ix11.
Warning Following Error
The warning following error signal goes true when any axis in the addressed coordinate system exceeds
its warning following error limit as set by Ix12.
Host Request
The host-request signal goes true when the PMAC2 is ready to read or write another character over the
PC bus. The user can select by writing to the base address of the PMAC2 whether the host request signal
reflects write-ready only, read-ready only, or both. Writing a 0 to the PMAC2 base address disables
generation of the host-request signal; writing a 1 enables the signal for host read-ready only; writing a 2
enables the signal for host write-ready only; writing a 3 enables the signal for both.
Position Compare 1 (EQU1)
The EQU1 signal goes true as toggled by the position compare registers and/or the direct-write feature of
the position compare function. The direct-write feature permits the use of this signal as a software-
generated interrupt from PMAC2 programs. With the suggested M-variable definitions, the code to
trigger a software-generated interrupt is: