Reference Manual

PMAC 2 Software Reference
418 PMAC I/0 and Memory Map
PMAC(1) DSPGATE Servo IC Registers
The registers in PMAC(1)’s “DSPGATE” Gate-Array ICs are mapped into the memory space of PMAC’s
processor. Each DSPGATE contains four consecutively numbered channels; there may be up to 4
DSPGATEs in a PMAC system, for up to 16 channels. Every PMAC contains the first DSPGATE, which
has channels 1 through 4. If Option 1 is ordered (not available on PMAC-Lite or Mini-PMAC), the
second DSPGATE is provided, which has channels 5 through 8. If an Accessory 24P/V or ACC-51P is
attached, the third DSPGATE is provided, which has channels 9 through 12. If Accessory 24P/V Option
1, or a second ACC-51P is attached as well, the fourth DSPGATE is provided, which has channels 13
through 16.
Enc #
1 2 3 4 5 6 7 8
Hex
[$C000] [$C004] [$C008] [$C00C] [$C010] [$C014] [$C018] [$C01C]
Decimal
49152 49156 49160 49164 49168 49172 49176 49180
Enc #
9 10 11 12 13 14 15 16
Hex
[$C020] [$C024] [$C028] [$C02C] [$C030] [$C034] [$C038] [$C03C]
Decimal
49184 49188 49192 49196 49200 49204 49208 49212
Y:$Cxxx
Time between last two encoder counts (SCLK cycles)
X:$Cxxx
Encoder Status/Control Bits (Bits 0-15: control; Bits
16-23: status – read-only)
0-3 Decode control (Encoder I-Variable 0)
4-7 Position capture control (Encoder I-Variable 2)
8-9 Flag select control (Encoder I-Variable 3)
10 Count write enable (when = 1, value written to compare
register is copied to counter)
11 Compare equal flag latch control
12 Compare-equal output enable
13 EQU output invert enable
14 AENAn output value
15 Digital delay filter disable (Encoder I-Variable 1)
16 Compare-equal flag
17 Position-captured flag
18 Count-error flag (latched to 1 on illegal count transition,
cleared to 0 on write to counter)
19 Encoder C channel input value
20 HMFLn input value
21 -LIMn input value
22 +LIMn input value
23 FAULTn input value
Enc #
1 2 3 4 5 6 7 8
Hex
[$C001] [$C005] [$C009] [$C00D] [$C011] [$C015] [$C019] [$C01D]
Decimal
49153 49157 49161 49165 49169 49173 49177 49181
Enc #
9 10 11 12 13 14 15 16
Hex
[$C021] [$C025] [$C029] [$C02D] [$C031] [$C035] [$C039] [$C03D]
Decimal
49185 49189 49193 49197 49201 49205 49209 49213
Y:$Cxxx
Time since last encoder count (SCLK cycles)
X:$Cxxx
Encoder phase position (counts)