Reference Manual

PMAC 2 Software Reference
144 PMAC I-Variable Specifiation
I9n5 Channel n Encoder Index Gate State/Demux Control {PMAC2 only}
Range
0 - 3
Units
none
Default
0
Remarks
I9n5 is a 2-bit variable that controls two functions for the index channel of the encoder.
When using the “gated index” feature of a PMAC2 Servo IC for more accurate position
capture (I9n4=1), bit 0 of I9n5 specifies whether the raw index-channel signal fed into
Encoder n is passed through to the position capture signal only on the “high-high”
quadrature state (bit 0 = 0), or only on the “low-low” quadrature state (bit 0 = 1).
Bit 1 of I9n5 controls whether the Servo IC “de-multiplexes” the index pulse and the 3
hall-style commutation states from the third channel based on the quadrature state, as with
Yaskawa incremental encoders. If bit 1 is set to 0, this de-multiplexing function is not
performed, and the signal on the “C” channel of the encoder is used as the index only. If
bit 1 is set to 1, the Servo IC breaks out the third-channel signal into four separate values,
one for each of the four possible AB-quadrature states. The de-multiplexed hall
commutation states can be used to provide power-on phase position using Ix81.
Note: The “B” revision or newer of the DSPGATE1 Servo IC is required to support this
hall de-multiplexing feature.
Note: Immediately after power-up, the Yaskawa encoder automatically cycles its AB
outputs forward and back through a full quadrature cycle to ensure that all of the hall
commutation states are available to the controller before any movement is started.
However, if the encoder is powered up at the same time as the PMAC2, this will happen
before the Servo IC is ready to accept these signals. Bit 2 of the channel’s status word,
“Invalid De-multiplex”, will be set to 1 if the Servo IC has not seen all of these states when
it was ready for them. To use this feature, it is recommended that the power to the encoder
be provided through a software-controlled relay to ensure that valid readings of all states
have been read before using these signals for power-on phasing.
I9n5 has the following possible settings:
• I9n5 = 0: Gate index with “high-high” quadrature state (GI = A & B & C), no demux
• I9n5 = 1: Gate index with “low-low” quadrature state (GI = A/ & B/ & C), no demux
• I9n5 = 2 or 3: De-multiplex hall and index from third channel, gating irrelevant
Note: Prior to firmware revision V1.17C, I9n5 was a single-bit I-variable controlling the
gating state only. The control bit for the de-multiplexing function had to be accessed
directly with an M-variable (it was stored to flash on a SAVE command and restored on
power-up/reset).
I9n6 Output n Mode Select {PMAC2 only}
Range
0 .. 3
Units
none
Default
0
Remarks
0 = Outputs A & B are PWM; Output C is PWM
1 = Outputs A & B are DAC; Output C is PWM
2 = Outputs A & B are PWM; Output C is PFM
3 = Outputs A & B are DAC; Output C is PFM
I9n6 controls what output formats are used on the command output signal lines for