Reference Manual

PMAC 2 Software Reference
PMAC I-Variable Specification 141
The clockwise (CW) and counterclockwise (CCW) options simply control which direction
counts up. If you get the wrong direction sense, simply change to the other option (e.g.
from 7 to 3 or vice versa).
Note:
Changing the direction sense of the decode for the feedback encoder
of a motor that is operating properly will result in unstable positive
feedback and a dangerous runaway condition in the absence of other
changes. The output polarity must be changed as well to re-
establish polarity match for stable negative feedback.
In the pulse-and-direction decode modes, PMAC2 is expecting the pulse train on CHAn,
and the direction (sign) signal on CHBn. If the signal is unidirectional, the CHBn line can
be allowed to pull up to a high state, or it can be hardwired to a high or low state.
If I9n0 is set to 8, the decoder inputs the pulse and direction signal generated by Channel
n’s pulse frequency modulator (PFM) output circuitry. This permits the PMAC2 to create
a phantom closed loop when driving an open-loop stepper system. No jumpers or cables
are needed to do this; the connection is entirely within the ASIC. The counter polarity
automatically matches the PFM output polarity.
If I9n0 is set to 11 or 15, the decoder looks at the 3-phase inputs on CHAn, CHBn, and
CHCn, and decodes 6 states per cycle. This permits the use of hall-style commutation
sensors for feedback. Each signal should be about 50% duty cycle, and 1/3-cycle offset
from the other signals. The direction sense of the decode changes between I9n0 = 11 and
I9n0 = 15. This mode is only supported on “B” and newer revisions of the DSPGATE1
IC.
If I9n0 is set to 12, the timer circuitry is set up to read magnetostrictive linear displacement
transducers (MLDTs) such as Temposonics
TM
. In this mode, the timer is cleared when the
PFM circuitry sends out the excitation pulse to the sensor on PULSEn, and it is latched
into the memory-mapped register when the excitation pulse is received on CHAn.
I9n1 Position Compare n Channel Select {PMAC2 only}
Range
0 .. 1
Units
None
Default
0
Remarks
I9n1 controls which encoder counter that Channel n’s position compare circuitry operates
with. When I9n1 is set to 0, the channel’s position compare register is tied to the channel’s
own encoder counter, and the position compare signal appears only on the EQUn output.
When I9n1 is set to 1, the channel’s position compare register is tied to the first encoder
counter on the ASIC – Encoder 1 for channels 1-4, or Encoder 5 for channels 5-8 – and the
position compare signal appears both on EQUn, and combined into the EQU output for the
first channel on the IC (EQU1 or EQU5); executed as a logical OR.
I911 and I951 perform no effective function, so are always 1. They cannot be set to 0.