Reference Manual

PMAC-PCI Hardware Reference
58 Software Setup
For a PMAC2 board with a saved value of 0 for I46, the serial baud rate is determined by the
combination of I54 and the CPU frequency on a PMAC2 board as shown in the following table.
These settings maintain backward compatibility.
I54 Baud Rate for
40 MHz CPU
Baud Rate for
60 MHz CPU
Baud Rate for
80 MHz CPU
0 600 DISABLED 1200
1 900* (-0.05%) 900 1800* (-0.1%)
2 1200 1200 2400
3 1800* (-0.1%) 1800 3600* (-0.19%)
4 2400 2400 4800
5 3600* (-0.19%) 3600 7200* (-0.38%)
6 4800 4800 9600
7 7200* (-0.38%) 7200 14,400*(-0.75%)
8 9600 9600 19,200
9 14,400*(-0.75%) 14,400 28,800*(-1.5%)
10 19,200 19,200 38,400
11 28,800*(-1.5%) 28,800 57,600*(-3.0%)
12 38,400 38,400 76,800
13 57,600*(-3.0%) 57,600 115,200*(-6.0%)
14 76,800 76,800 153,600
15 DISABLED 115,200 DISABLED
* Not an exact baud rate
• With the Flex CPU, the card number (0 – 15) for serial addressing of multiple cards on a daisy-
chain serial cable is determined by variable I0, even on PMAC(1) boards. This has always been
the case for PMAC2 boards, but with other CPU boards, the card number on PMAC(1) boards
has been determined by the settings of jumpers E40 – E43. Jumpers E40 – E43 on a PMAC(1)
board with the Flex CPU still determine the “direction” of the phase and servo clocks: all of these
jumpers must be ON for the card to use its internally generated clock signals and to output these
on the serial port connector; if any of these jumpers is OFF, the card will expect to input these
clock signals from the serial port connector, and its watchdog timer will trip immediately if it
does not receive these signals.
Configuring PMAC with Option-5C for 80 MHz Operation
On a PMAC with flash-backed main memory, jumper E48 controls the frequency of operation of the
DSP. It can only directly set 40 MHz and 60 MHz DSP operation. On power-up/reset, the DSP,
operating at the crystal frequency of 20 MHz, reads the frequency jumper E48 and writes into its own
PLL multiplier register at X:$FFFD. Bits 0-3 of this word contain a value one less than the multiplier
value (if the frequency is being multiplied by 3, these bits contain a value of 2).