Datasheet

DS_IPM24S0C0_01092009
6
TEST CONFIGURATIONS
V I (+)
V I (-)
BATTERY
2
100uF
Electrolytic
L
Ceramic
3.3uF
Note: Input reflected-ripple current is measured with a
simulated source inductance. Current is
measured at the input of the module.
Figure 15: Input reflected-ripple current test setup
Vo
GND
100uFx2
OS-con
1uF
ceramic
SCOPE
Resistive
Load
Note: Use a 100μFx2 OS-son and 1μF capacitor. Scope
measurement should be made using a BNC
connector.
Figure 16: Peak-peak output noise and startup transient
measurement test setup
VI Vo
GND
Figure 17: Output voltage and efficiency measurement test
setup
Note: All measurements are taken at the module
terminals. When the module is not soldered (via
socket), place Kelvin connections at module
terminals to avoid measurement errors due to
contact resistance.
%100)( 



IiVi
IoVo

DESIGN CONSIDERATIONS
Input Source Impedance
To maintain low-noise and ripple at the input voltage, it is
critical to use low ESR capacitors at the input to the
module. Figure 26 shows the input ripple voltage
(mVp-p) for various output models using 2x100uF low
ESR electrolytic capacitors (Rubycon P/N:50YXG100,
100uF/50V or equivalent) and 1x3.3.0 uF very low ESR
ceramic capacitors (TDK P/N: C4532JB1H335M,
3.3uF/50V or equivalent).
The input capacitance should be able to handle an AC
ripple current of at least:
Arms
Vin
Vout
Vin
Vout
IoutIrms






 1
Figure 18: Input ripple voltage for various output models,
Io = 3A (Cin =2x100uF electrolytic capacitors
1x3.3uF ceramic capacitors at the input)
The power module should be connected to a low
ac-impedance input source. Highly inductive source
impedances can affect the stability of the module. An
input capacitance must be placed close to the modules
input pins to filter ripple current and ensure module
stability in the presence of inductive traces that supply
the input voltage to the module.