Datasheet

DS_DNM10SMD10_07182012
6
TEST CONFIGURATIONS
VI(+)
VI(-)
BATTERY
2
100uF
Tantalum
L
TO OSCILLOSCOPE
Note: Input reflected-ripple current is measured with a
simulated source inductance. Current is
measured at the input of the module.
Figure 17: Input reflected-ripple test setup
Vo
GND
COPPER STRIP
10uF
tantalum
1uF
ceramic
SCOPE
Resistive
Load
Note: Use a 10μF tantalum and 1μF capacitor. Scope
measurement should be made using a BNC
connector.
Figure 18: Peak-peak output noise and startup transient
measurement test setup
SUPPLY
I
VI Vo
GND
Io
LOAD
CONTACT AND
DISTRIBUTION LOSSES
CONTACT RESISTANCE
Figure 19: Output voltage and efficiency measurement test
setup
Note: All measurements are taken at the module
terminals. When the module is not soldered (via
socket), place Kelvin connections at module
terminals to avoid measurement errors due to
contact resistance.
%100)( 



IiVi
IoVo

DESIGN CONSIDERATIONS
Input Source Impedance
To maintain low-noise and ripple at the input voltage, it is
critical to use low ESR capacitors at the input to the
module. Figure 20 shows the input ripple voltage
(mVp-p) for various output models using 4x47 uF low
ESR tantalum capacitors (SANYO P/N:16TPB470M,
47uF/16V or equivalent) and 4x22 uF very low ESR
ceramic capacitors (TDK P/N:C3225X7S1C226MT,
22uF/16V or equivalent).
The input capacitance should be able to handle an AC
ripple current of at least:
Arms
Vin
Vout
Vin
Vout
IoutIrms






 1
0
50
100
150
200
250
300
0 1 2 3 4 5 6
Output Voltage (Vdc)
Input Ripple Voltage (mVp-p)
Tantalum
Ceramic
Figure 20: Input ripple voltage for various Output models,
Io = 10A (Cin = 4x47uF tantalum capacitors and
4x22uF ceramic capacitors at the input)