Datasheet

DS_DIM3R3400_08142013 E-mail: [e-mail]
http://www.deltaww.com/dcdc
P11
I2C DATA REPORTING INTERFACE:
The module has a digital I2C Serial interface to allow the
module to be monitored by the system. The module
supports 3 I2C signal lines, Data, Clock and 1 Address
line I2C_ADR. the Delta I2C Serial Interface monitors 5
analog parameters and 6 status bits. The actual analog
parameter values are calculated by multiplying by the
specified scaling factors (see table1). The status bits are
interpreted in Table 2. The initial value of all registers is
zero. Data in the registers begins updating 300ms after
management power startup, and continues updating at
approximately 100ms intervals during steady-state
operation. All registers are updated simultaneously. The
I2C_DAT and the I2C_CLK have been pull high to
internal 3.3V.
Table 1: Internal register memory map.
Table 2: The status byte represents 6 different digital
signals and their digital state.
Note: 1)Bit0=>LSB, Bit7=>MSB
I2C PROTOCOL:
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a sin-
gle Read/Write bit, which determines whether the mas-
ter intends to transmit to or receive data from the slave
device.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode,
respectively.
A Start bit is indicated by a high-to-low transition of the
SDAx line while the SCLx line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
responds after each byte with an ACK bit. In this
example, the master device is in Master Receive mode
and the slave is Slave Transmit mode.
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is
indicated by a low-to-high transition of the SDAx line
while the SCLx line is held high.
Reading from any internal register of the Delta monitor
requires that an internal register, Data_Pointer, be
initialized prior to reading (see Figure 16).
Figure 16: Typical I2C read transmission. Note: S = START,
W = WRITE, R = READ, AK = acknowledged, NACK = NOT
acknowledged, P = STOP. Clear boxed originate in the I2C
Master and shaded boxed originate in the I2C Slave.