User's Manual

DFZM-TS2xx
Data Sheet Sheet 8 of 37 AUG 22, 2013
Proprietary Information and Specifications are Subject to Change
3-2.Block Diagram Description
3-2-1.Overview
DFZM-TS2xx module is a highly integrated Zigbee system-on-chip (SOC) that contains the following:
• The module includes TI CC2530 SoC, which contains CPU- and memory-related, peripherals-related, clocks
and power management-related in a single package.
• The module features an IEEE802.15.4-compliant radio transceiver with onboard 32 KHz & 32 MHz crystal
circuitries, RF, and certified chip antenna or external antenna options.
o The low power module option has a capability of +4.5dBm output power at the antenna (see
Figure 3-1).
o The high power module option has a capability of +18.5dBm output power at the antenna (see
Figure 3-2).
• Variety of interfaces are available such as two USART and SPI, four TIMER, one 7~12 bit ADC,
Operational amperifier and GPIO.
• DFZM-TS2xx contains single power supply (VCC).
3-2-2.CPU and Memory
The 8051 CPU core used in the CC253x device family is a single-cycle 8051-compatible core. It has three
different memory-access buses (SFR, DATA and CODE/XDATA) with single-cycle access to SFR, DATA, and
the main SRAM. It also includes a debug interface and an 18-input extended interrupt unit.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is
in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode (power
modes 1–3).
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory access points, access of
which can map to one of three physical memories: an 8-KB SRAM, flash memory, and XREG/SFR registers. It
is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same