Datasheet

DS_DCM12S0A0S12NFA_06092014 E-mail: [e-mail]
http://www.deltaww.com/dcdc
P10
TEST CONFIGURATIONS
Figure 37: Input reflected-ripple test setup
Vo
GND
10uF
tantalum
1uF
ceramic
SCOPE
Resistive
Load
Note: Use a 10μF tantalum and 1μF capacitor. Scope
measurement should be made using a BNC connector.
Figure 38: Peak-peak output noise and startup transient
measurement test setup.
VI Vo
GND
Figure 39: Output voltage and efficiency measurement test
setup
Note: All measurements are taken at the module terminals.
When the module is not soldered (via socket), place
Kelvin connections at module terminals to avoid
measurement errors due to contact resistance.
%100)( 



IiVi
IoVo

DESIGN CONSIDERATIONS
Input Source Impedance
To maintain low noise and ripple at the input voltage, it is
critical to use low ESR capacitors at the input to the
module. A highly inductive source can affect the stability
of the module. An input capacitance must be placed close
to the modules input pins to filter ripple current and ensure
module stability in the presence of inductive traces that
supply the input voltage to the module.