Datasheet

DS_DCL12S0A0S20NFA_06182014 E-mail: [e-mail]
http://www.deltaww.com/dcdc
P12
FEATURE DESCRIPTIONS (CON.)
Voltage Margining
Output voltage margining can be implemented in the DCL
modules by connecting a resistor, R margin-up, from the Trim pin
to the ground pin for margining-up the output voltage and by
connecting a resistor, Rmargin-down, from the Trim pin to the
output pin for margining-down. Figure 35 shows the circuit
configuration for output voltage margining. If unused, leave the
trim pin unconnected. A calculation tool is available from the
evaluation procedure which computes the values of Rmargin-up
and Rmargin-down for a specific output voltage and margin
percentage.
Figure 35: Circuit configuration for output voltage margining
Output Voltage Sequencing
The DCL 12V 20A modules include a sequencing feature,
EZ-SEQUENCE that enables users to implement various types of
output voltage sequencing in their applications. This is
accomplished via an additional sequencing pin. When not using
the sequencing feature, either tie the SEQ pin to VIN or leave it
unconnected.
When an analog voltage is applied to the SEQ pin, the output
voltage tracks this voltage until the output reaches the
set-point voltage. The final value of the SEQ voltage must be
set higher than the set-point voltage of the module. The output
voltage follows the voltage on the SEQ pin on a one-to-one
basis. By connecting multiple modules together, multiple
modules can track their output voltages to the voltage applied
on the SEQ pin.
For proper voltage sequencing, first, input voltage is applied to
the module. The On/Off pin of the module is left unconnected
(or tied to GND for negative logic modules or tied to VIN for
positive logic modules) so that the module is ON by default.
After applying input voltage to the module, a minimum 10msec
delay is required before applying voltage on the SEQ pin. This
delay gives the module enough time to complete its internal
power-up soft-start cycle. During the delay time, the SEQ pin
should be held close to ground (nominally 50mV ± 20 mV).
This is required to keep the internal op-amp out of saturation
thus preventing output overshoot during the start of the
sequencing ramp. By selecting resistor R1 (see Figure. 37)
according to the following equation









05.0
24950
1
Vin
R
Figure 36: Sequential Start-up
The voltage at the sequencing pin will be 50mV when the
sequencing signal is at zero.