Integration Guide
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 SIM interface
- 1.9 Serial Communication
- 1.10 Audio
- 1.11 ADC input (LEON-G100 only)
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 M2M Setup Schematic Example
- 1.14 Approvals
- 2 Design-In
- 3 Handling and soldering
- 4 Product Testing
- Appendix
- A Extra Features
- B Glossary
- Related documents
- Revision history
- Contact
LEON-G100/G200 - System Integration Manual
GSM.G1-HW-09002-F3 Preliminary Design-In
Page 71 of 101
2 Design-In
2.1 Design-in checklist
This section provides a design-in checklist.
2.1.1 Schematic checklist
The following are the most important points for a simple schematic check:
DC supply must provide a nominal voltage at VCC pin above the minimum normal operating range limit.
DC supply must be capable to provide 2.5 A current bursts with maximum 400 mV voltage drop at VCC
pin.
VCC supply should be clean, with very low ripple/noise: suggested passive filtering parts can be inserted.
Connect only one DC supply to VCC: different DC supply systems are mutually exclusive.
V_CHARGE and CHARGE_SENSE must be externally shorted (LEON-G200 only).
The DC supply used as charger must be voltage and current limited as specified (LEON-G200 only).
Do no leave PWR_ON floating: add a pull-up resistor to a proper supply (i.e. V_BCKP or VCC).
Check that voltage level of any connected pin does not exceed the relative operating range.
Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications.
Insert the suggested low capacitance ESD protection and passive filtering parts on each SIM signal.
Check UART signals direction, since the signal names follow the ITU-T V.24 Recommendation [4].
Add a proper pull-up resistor to a proper supply on each DDC (I
2
C) interface line, if the interface is used.
Capacitance and series resistance must be limited on each line of the DDC interface.
Insert the suggested passive filtering parts on each used analog audio line.
Check the digital audio interface specifications to connect a proper device.
For debug purposes, add a test point on each I
2
S pin and on GPIO1 also if they are not used.
To avoid an increase of module current consumption in power down mode, any external signals
connected to the module digital pins (UART interface, HS_DET, GPIOs) must be set low or tri-stated
when the module is in power down mode.
Any external signal connected to the digital audio interface must be tri-stated when the module is in
power down mode and must be tri-stated during the module power-on sequence (at least for 1500 ms
after the start-up event).
Provide proper precautions for ESD immunity as required on the application board.
All the not used pins can be left floating on the application board.
2.1.2 Layout checklist
The following are the most important points for a simple layout check:
Check 50 Ω impedance of ANT line.
Follow the recommendations of the antenna producer for correct antenna installation and deployment.
Ensure no coupling occurs with other noisy or sensitive signals.
VCC line should be wide and short.
Route VCC supply line away from sensitive analog signals.
Avoid coupling of any noisy signals to microphone inputs lines.
Ensure proper grounding.
Consider “No-routing” areas for the Data Module footprint.