Users Guide

Manage clock selection
Clock synchronization depends to a large extent on QL or priority of the clock sources. However, you can influence clock
selection by modifying the following clock properties:
● Force switch—The switch forcibly selects a clock source regardless of its availability or quality. Use the sync-e switch
force command to override the currently selected synchronization source. Ensure that the new source clock is enabled and
is not locked out. Use the clear sync-e switch command to clear the force switch command.
● Manual switch—The switch selects a synchronization source that is in enabled state, not locked out, not in signal fail
condition, and has a QL better than Do Not Use (DNU) in QL-enabled mode. In QL-enabled mode, a manual switch is
performed only to a source that has the highest available QL. Use the sync-e switch manual command to initiate a
manual switch. Use the clear sync-e switch command to clear the manual switch command.
● Lockout—The clock source is locked and it is not available for the selection process. Use the sync-e lockout command
to lock a clock source on an interface. Use the clear sync-e lockout command to clear the lockout state of an
interface so that the clock source on that interface can be considered for selection process.
● Hold-Off Time—When a clock source goes down, the switch waits for the configured hold-off time period before removing
the clock source from the clock selection process. The default time period is 300 milliseconds. Use the sync-e hold-
off-time command to configure the hold-off time.
● Wait-to-Restore Time—The amount of time that the switch waits before considering a previously failed synchronization
source as available for the selection process, if it is fault free for the configured time period. The default time period is 300
seconds. Use the sync-e wait-to-restore-time command to configure the wait-to-restore time. Use the clear
sync-e wait-restore-time command to stop the remaining timer and allow the ports to participate in clock selection.
Standby clock source states
Under normal circumstances, all network elements are synced to the active clock source. If the active clock source becomes
faulty, a reference source from the available standby clock sources is selected based on the selection algorithm. The standby
clock sources work in any of the following states:
● Available—The clock source is operationally up.
● Failed—The clock source is in signal fail state or the SyncE-enabled interfaces do not receive any clock signal. This state can
be caused due to link failure, ESMC timeout, or frequency recovery failure.
● Locked—The clock source is not available for the selection process.
● Wait-to-Restore—The clock source has recovered from the signal fail state and is waiting for the wait-to-restore interval to
expire so that it can participate in the clock selection process.
● Holdover—The lock status of a system clock when it is not synchronized to any of the reference clock sources.
● Free Run—The temporary state until a valid source is available.
● Acquiring—The state of acquiring lock before moving to either frequency locked or holdover state.
Restrictions and limitations
● SNMP MIBs for ESMC statistics and SyncE events are not supported.
● In a link aggregation group (LAG), the SyncE configuration is supported only on the member ports of the LAG. SyncE
configuration is not supported on the LAG.
● SyncE is supported only on some specific optics. See Appendix III of ITU G.8262 standard for the list of SyncE compatible
interfaces.
● SyncE is not supported on the following 10G SFP+ ports on S5232F-ON platform: 33 and 34. Hence, these ports cannot be
used for recovering clock frequency.
● 1G ports are not supported for recovering clock frequency even though an in-accurate clock frequency recovery is possible.
Hence, Dell Technologies recommend not to use 1G ports for SyncE.
Sample configurations
The following figure shows a simple topology with SyncE enabled switches, Switch A and Switch B connected to each other
through a back-to-back interface. The external clock source SRC-1 is configured with quality level SSU-A, and SRC-2 is
configured with quality level PRC.
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System management