Release Notes

6 Balanced Memory with 2

Generation AMD EPYC

Processors for PowerEdge Servers

3. Memory Interleaving

Memory interleaving allows a CPU to efficiently spread memory accesses across

multiple DIMMs. When memory is put in the same interleave set, contiguous memory

accesses go to different memory banks. Memory accesses no longer must wait until the

prior access is completed before initiating the next memory operation. For most

workloads, performance is maximized when all DIMMs are in one interleave set creating

a single uniform memory region that is spread across as many DIMMs as possible.

Multiple interleave sets create disjointed memory regions.

3.1 NPS and Quadrant Pairing

Rome processors achieve memory interleaving by using Non-Uniform Memory Access

(NUMA) in Nodes Per Socket (NPS).

There are four NPS options available in the Dell

EMC BIOS:

1. NPS 0 – One NUMA node per system (on two processors systems only). This

means all channels in the system are using one interleave set.

2. NPS 1 – One NUMA node per socket (on one processor systems). This means all

channels in the socket are using one interleave set.

3. NPS 2 – Two NUMA nodes per socket (one per left/right half). This means each

half containing four channels is using one interleave set; a total of two sets.

4. NPS 4 – Up to four NUMA nodes per socket (one per quadrant). This means each

quadrant containing two channels is using one interleave set; a total of four sets.

The simplest visual aid for understanding the NPS system is to divide the CPU into four

quadrants. We see below in Figure 2 that each quadrant contains two paired DIMM

channels that can host up to two DIMMs. The paired DIMM channels in each quadrant

were designed to group and minimize the travel distance for interleaved sets. NPS 1

would correlate to all four quadrants being fully populated. NPS 2 would correlate to

having either the left or right half quadrant being fully populated. NPS 4 would correlate

to having any one quadrant being fully populated.

Figure 2: Quadrant layout of Rome processors