Concept Guide

5 Memory Errors and Dell PowerEdge YX4X Server Memory RAS Features
Unconsumed
Poisoned upon detection;
error waits to be consumed
Error waits to be consumed
A Primer on Dell EMC PowerEdge Server Memory RAS Capabilities
Previously discussed memory errors are mitigated through PowerEdge server memory RAS capabilities
which entail fault avoidance, detection, and correction in hardware and software. These mitigating RAS
features are all intended to improve system reliability and extend uptime in the event of memory errors.
FYI: It is useful to understand the difference between x4 and x8 DIMMs. This
refers to the width of the DRAM components on a memory module. x4 DIMMs
utilize DRAM components that have a 4-bit data width and x8 DIMMs utilize
components with an 8-bit data width.
The common DIMM organizational notation is as follows: #RxN. Where # is the
number of ranks and N is the width of the DRAM. Example – 2Rx4 means the
DIMM has two ranks of x4 DRAM devices.
Single Error Correction - Double Error Detection (SEC-DED) ECC
SEC-DED Feature Support Table
DIMMs Supported
x4 DIMMs: 
x8 DIMMs: 
Single Error Correction - Double Error Detection ECC, or SEC-DED ECC, is the most basic form of error
correcting code (ECC) available. All PowerEdge servers configured with ECC memory modules are
capable of SEC-DED for each memory page access (64 data bits + 8 ECC bits). This means that any one bit
among the 72-bits accessed from DRAM can be incorrect and PowerEdge server hardware will
automatically correct it – regardless of cause.
Advanced ECC
Advanced ECC Feature Support Table
DIMMs Supported
x4 DIMMs: 
(Use of x4 DIMMs May Provide DRAM Device Correction)
x8 DIMMs: 
(Use of x8 DIMMs May Provide Nibble Correction)
Advanced ECC is a RAS feature that provides error correction on single-bit and multi-bit failures that are
bound within 4-bits (nibble) of memory accesses. When used in conjunction with DIMMs based on x4
DRAM devices, Advanced ECC may provide error correction to an entire single DRAM device. This type of
error correction that covers an entire DRAM device has been branded in various forms, most
popularized as Chipkill and Single Device Data Correction (SDDC). Advanced ECC is a highly complex