Deployment Guide

System BIOS
26 Setting up BIOS on 15th Generation (15G) Dell EMC PowerEdge Servers | 508
L1 Region
Prefetcher
• Enabled
• Disabled
When set to Enabled, the processor provides additional
fetch to data along with the data access to the given
instruction for performance tuning by controlling the L1
region prefetcher setting. This setting can affect
performance based on the application and workloads
running on the system.
Note: This option is only available on systems with AMD
processors.
L2 Up Down
Prefetcher
• Enabled
• Disabled
When set to Enabled, the processor uses memory access to
determine whether to fetch next or previous for all memory
accesses for advanced performance tuning by controlling
the L2 up/down prefetcher setting. This setting can affect
performance based on the application and workloads
running on the system.
Note: This option is only available on systems with AMD
processors.
DCU Streamer
Prefetcher
• Enabled
• Disabled
Allows you to enable or disable the Data Cache Unit (DCU)
streamer prefetcher. This setting can affect performance
based on the application and workloads running on the
system. Recommended for High Performance Computing
applications.
DCU IP
Prefetcher
• Enabled
• Disabled
Allows you to enable or disable the Data Cache Unit (DCU)
IP prefetcher. This setting can affect performance based on
the application and workloads running on the system.
Recommended for High Performance Computing
applications.
Sub NUMA
Cluster
• Enabled
• Disabled
Sub NUMA Clustering (SNC) is a feature for breaking up the
LLC into disjoint clusters based on address range, with each
cluster bound to a subset of the memory controllers in the
system. It improves average latency to the LLC.
MADT Core
Enumeration
• Round Robin
• Linear
This field determines how BIOS enumerates processor
cores in the ACPI MADT table.
When set to Round Robin, Processor cores are enumerated
in a Round Robin order to evenly distribute interrupt
controllers for the OS across all Sockets and Dies.
When set to Linear, Processor cores are enumerated across
all Dies within a Socket before enumerating additional
Sockets for a linear distribution of interrupt controllers for
the OS.
Note: This option is only available on systems with AMD
processors.
NUMA Nodes
Per Socket
• 0
• 1
• 2
• 4
This field specifies the number of NUMA nodes per socket.
The Zero option is for 2 socket configurations.
Note: This option is only available on systems with AMD
processors.