Deployment Guide

System BIOS
25 Setting up BIOS on 15th Generation (15G) Dell EMC PowerEdge Servers | 508
Address
Translation
Services
(ATS)
• Enabled
• Disabled
Defines the Address Translation Cache (ATC) behavior for
devices to cache DMA translations. This field provides an
interface to a chipset's Address Translation and Protection
Table to translate DMA addresses to host addresses.
Directory
Mode
• Enabled
• Disabled
Defines the Address Translation Cache (ATC) behavior for
devices to cache DMA translations. This field provides an
interface to a chipset's Address Translation and Protection
Table to translate DMA addresses to host addresses.
Note: This option is only available on systems with Intel
processors.
Adjacent
Cache Line
Prefetch
• Enabled
• Disabled
Enables you to optimize the system for applications that
require high utilization of sequential memory access. You
can disable this option for applications that require high
utilization of random memory access.
Hardware
Prefetcher
• Enabled
• Disabled
When enabled, the processor is able to prefetch extra cache
lines for every memory request. This setting can affect
performance based on the application and workloads
running on the system and memory bandwidth utilization.
Software
Prefetcher
• Enabled
• Disabled
When set to Enabled, the processor provides advanced
performance tuning by controlling the software prefetcher
setting. This setting can affect performance based on the
application and workloads running on the system. .
Note: This option is only available on systems with AMD
processors.
L1 Stream HW
Prefetcher
• Enabled
• Disabled
When set to Enabled, the processor provides advanced
performance tuning by controlling the L1 stream HW
prefetcher setting. This setting can affect performance
based on the application and workloads running on the
system
Note: This option is only available on systems with AMD
processors.
L2 Stream HW
Prefetcher
• Enabled
• Disabled
•
When set to Enabled, the processor provides advanced
performance tuning by controlling the L2 stream HW
prefetcher setting. This setting can affect performance
based on the application and workloads running on the
system
Note: This option is only available on systems with AMD
processors.
L1 Stride
Prefetcher
• Enabled
• Disabled
When set to Enabled, the processor provides additional
fetch to the data access for an individual instruction for
performance tuning by controlling the L1 stride prefetcher
setting. This setting can affect performance based on the
application and workloads running on the system
Note: This option is only available on systems with AMD
processors.