Specifications

0x3e : CPLD4
0x0 : SMF_FPGA
read output
root@dell-diag-os:~# pltool --read --devname=CPLD4 --dev=0x3e --reg=0x2
SW_SCRATCH : offset 0x02 = 0xde
7: 0 SW_SCRATCH = de
root@dell-diag-os:~#
write output
root@dell-diag-os:~# pltool --write --devname=CPLD4 --dev=0x3e --reg=0x2 --val=0xff
test output
root@dell-diag-os:~# pltool --test
Testing Programmable Devices:
PL Tool test:
CPLD1 .................... Passed
CPLD2: SW_SCRATCH.................... Passed
CPLD3: SW_SCRATCH.................... Passed
CPLD4: SW_SCRATCH.................... Passed
SMF_FPGA ............................ Passed
PL Tool: Overall test results ---- >>> Passed
Conguration le format
The pltool uses the device tree conguration format.
# C - CHIP (Master | Slave - Cpld or FPGA), Address, Name, Access
# R - Register, Offset, Mask, Name, RW , Default Val
# B - Bit(s), bitnum(s), Name, RW, Default Val
# I - Information on the bits
=====
C | CPLD | | CPLD1| lpc | 0 | - | U5 | 0x01 | 0xf
R | 0x100 | 8 | 0xFF | CPLD_VERSION | RO | 0x0 | 0 | 0x0
B | 7:4 | MAJOR_VER | RO | 0x0
B | 3:0 | MINOR_VER | RO | 0x0
R | 0x101 | 8 | 0xFF | BOARD_TYPE | RO | 0xFF | 0 | 0x0
B | 7:0 | BOARD_TYPE | RO | 0x01
I | 3 | <
platform> Board
R | 0x102 | 8 | 0xFF | SW_SCRATCH | RW | 0xDE | 1 | 0x0
B | 7:0 | SW_SCRATCH | RW | 0xDE
R | 0x103 | 8 | 0xFF | CPLD_ID | RO | 0xFF | 0 | 0x0
B | 7:0 | CPLD_ID | RO | 0x01
R | 0x10F | 8 | 0xFF | BOARD_REV | RO | 0xFF | 0 | 0x0
B | 7:0 | BOARD_REV | RO | 0x0
R | 0x110 | 8 | 0xFF | CPLD_SEP_RST0 | RO | 0xFF | 0 | 0x0
B | 7 | Reset Extender CPLD 4 | RW | 0x1
I | 0 | Reset
I | 1 | Not Reset
B | 6 | Reset Extender CPLD 3 | RW | 0x1
Dell EMC DiagOS tools
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