Administrator Guide

Configuration File Format
The configuration file for the memtool is a list of memory segments separated by a ==== divider. Each entry describes the
memory in a system that is accessible. This allows you to review memory in RAMs, FPGAs, and RAM in a memory-mapped PCI
BAR. Each parameter is on a separate line and consists of:
• Name — The name of the memory region.
• Start Address — The address that the memory starts with. If this is system memory, use a '-' to request the system to get
a location from the OS Heap.
• Size — The size of the memory. If this is system memory, use a '-' to request the system to get a location from the OS
Heap
• Access Mode — How you access the memory; through (b)yte, (h)alfword, or (w)ord.
• Increment — The byte address increment for each successive memory location.
• Ecc — checks if ECC is available.
• Max Chunk — Memory is tested in chunks in which the available memory is divided into. This is the maximum size of a
chunk.
• Max Cache — The size of the cache (not currently used). Ensures that caches are fully tested.
• Cache Line — The size of a cache line (not currently used).
• Iterations — How many times to run the tests on this region.
• Tests — lists the tests to perform. Tests are specified in a comma-separated list.
Available tests are:
• ALL_TESTS — All the following tests, except for DATA_CACHE, which must be run separately.
• ADDRESS_READ — Read test of the address lines.
• ADDRESS_WRITE — Write test of the address lines.
• ADDRESS_WALKING1 — Walking a 1 through the address lines within the memory space.
• ADDRESS_WALKING0 — Walking a 0 through the address lines within the memory space.
• DATA_READ — Read test of the data lines.
• DATA_WRITE — Write test of the data lines.
• DATA_WALKING1 — Walking a 1 through the data lines.
• DATA_WALKING0 — Walking a 0 through the data lines.
• DATA_SLIDING1 — Sliding a 1 through the data lines.
• DATA_SLIDING0 — Sliding a 0 through the data lines.
• DATA_PATTERN — Writing and reading patterns from the memory.
• DATA_CACHE — Exercises the RAM by completing cache evictions by rotating a very large array, usually cache-line size
square, of the values in memory multiple times.
• SPD Device — Not used.
• SPD Access — Bus to use to access the SPD.
• SPD Address — The address of the SPD chip (in hex) on the bus, if applicable.
• SPD Registers — The valid registers of the SPD chip listed as start,end.
SystemRam
Start Address:-
Size:-
Access Mode:w
Increment:4
Ecc:1
Max Chunk:2800
Max Cache:0
Cache Line:0
Iterations:1
Tests:ALL_TESTS
SPD Device:SPD
Dell DiagOS Tools 53