Reference Guide

Item
How is data input to this
memory?
How is this memory write
protected?
How is the memory
cleared?
3.5” HDD BP
FRU
Pre-programmed before
assembly.
Not WP.
User cannot clear the
memory.
CPLD A
Pre-programmed before
assembly or PM8056 flash
CPLD FW by I2C bus.
Not WP.
Use expander DUP to
update PM8056 & CPLD
FW.
CPLD B
Pre-programmed before
assembly or PM8056 flash
CPLD FW by I2C bus.
Not WP.
Use expander DUP to
update PM8056 & CPLD
FW.
MB bridge board
FRU
Pre-programmed before
assembly.
Not WP.
User cannot clear the
memory.
Power Delivery Board (PDB)
Microcontroller
Pre-programmed before
assembly. Can be updated
using pass through by
CM(JTAG/UART) tools
Not WP. Not visible to
Host Processor
Cannot be cleared with
existing tools available to
the customer
FRU
Programmed at BFT
during production.
Not WP.
Cannot be cleared with
existing tools available to
the customer
Flash
Pre-programmed before
assembly.
On-Line: It can be updated
using pass through by
CM(JTAG/UART) tools.
Off-Line: It can be updated
using pass through by
EEPROM copy machine
tools
Not WP. Not visible to
Host Processor
Cannot be cleared with
existing tools available to
the customer
FPGA
Pre-programmed before
assembly. Can be updated
using pass through by
CM(JTAG/UART) tools
Not WP. Not visible to
Host Processor
Cannot be cleared with
existing tools available to
the customer
Rover MB
PCH Internal
CMOS RAM
BIOS
N/A – BIOS only control
Perform the following
steps:
1) Set NVRAM_CLR
jumper to clear BIOS
configuration settings at
boot and reboot system.
2) AC power off system,
remove coin cell battery for
30 seconds, replace
battery and power on.
3) Restore default
configuration in F2 system
setup menu.
BIOS Password (part of PCH
internal CMOS RAM)
Keyboard
N/A – BIOS only control
1) Place shunt on
J_PSWD_NVRAM jumper
pins 2 and 4.
2) AC power off is required
after placing the shunt.
3) AC power on with the
shunt in place and then
can be removed.