Specifications

Dell
PowerEdge T310 Technical Guide
34
The 11
th
generation BIOS exposes the following power profiles in the BIOS setup.
Table 16. Power Profiles
Power Profile
Description
Static MAX Performance
Disable DBPM: BIOS sets P-State to MAX
Memory frequency = MAX
Fan algorithm = performance (UI)
OS /Hypervisor DBPM
Control
Enable OS DBPM Control: BIOS exposes all possible P-states to OS
Memory frequency = MAX
Fan algorithm = power
Active Power Controller
Enable Dell System DBPM (BIOS will not make all P states available to OS)
Memory frequency = MAX
Fan algorithm = power
Custom
CPU Power and Performance Management:
Max Performance | Minimum Power | OS DBPM | System DBPM
Memory Power and Performance Management:
Max Performance |1333MT/s |1067 MT/s |800 MT/s | Min Power
Fan Algorithm
Performance | Power
9.3 I2C Block Diagram
I
2
C is a simple bi-directional two-wire bus for efficient inter-integrated circuit control. All I
2
C-bus
compatible devices incorporate an on-chip interface which allows them to communicate directly with
each other via the I
2
C bus. This design concept solves the many interfacing problems encountered
when designing digital control circuits. These I
2
C devices perform communication functions between
intelligent control devices (such as microcontrollers), general-purpose circuits (such as LCD drivers,
remote I/O ports, memories) and application-oriented circuits.
The PowerEdge T310 BIOS accesses the I
2
C through the PCH (Intel Platform Controller Hub 3420).
There are two multiplexers (MUX) on the PCH I
2
C bus.
• One MUX (U60) controls the DIMM SPDs through four split segments.
• One MUX (U44) controls the clock, TOE, and USB Hub through four split segments.
The BIOS controls both the MUXes through the two select lines using GPIO pins. The clock chip, USB
hub, and the front panel EEPROM device addresses are located on the IOH I
2
C bus.