Reference Guide

Item
How is data input to this memory?
How is this memory write protected?
ONFI Backup Flash
FPGA backs up DDR data to this
device in case of a power failure
Not WP. Not visible to Host Processor
SDRAM
ROC writes to this memory - using it
as cache for data IO to HDDs
Not WP. Not visible to Host Processor
NVSRAM
ROC writes configuration data to
NVSRAM
Not WP. Not visible to Host Processor
Mid-plane Interface Module
FRU EEPOM
I2C interface via CMC.
HW write protected function is disable.
Storage Expander Module
NVSRAM
External Memory Bus interface via
LSI SAS3x24_UL chip.
No HW write protected function.
Flash ROM
Offline programmed/Online
programmed via LSI SAS3x24_UL.
HW write protected function is disable.
BP FRU EEPROM
I2C interface via CMC.
HW write protected function is disable.
SEM FRU EEPROM I2C interface via CMC. HW write protected function is disable.
NOTE: For any information that you may need, direct your questions to your Dell Marketing contact.
______________
© 2015 Dell Inc.
Trademarks used in this text: Dell™, the DELL logo, and PowerEdge™ are trademarks of Dell Inc.