Reference Guide

Item
How is data input to this memory?
How is this memory write protected?
Planar
PCH Internal CMOS RAM
BIOS
N/A – BIOS only control
BIOS Password
Keyboard
N/A
BIOS SPI Flash
SPI interface via host
Software write protected
iDRAC SPI Flash
SPI interface via iDRAC
Embedded iDRAC subsystem firmware
actively controls sub area based write
protection as needed.
iDRAC EMMC
NAND Flash interface via iDRAC
Embedded FW write protected
CPU
Various
Various
CPU VCORE regulators
N/A
N/A
Memory regulators
N/A
N/A
Embedded Network EEPROM
SPI interface via Intel i350 LOM
N/A
Embedded Network Flash
SPI interface via Intel i350 LOM
N/A
System CPLD RAM
Not utilized
Not accessible
SEP for 1.8” SSD Backplane
I2C interface via iDRAC
Program write protect bit
iDRAC
iDRAC Firmware
N/A
iDRAC DDR Memory
iDRAC Firmware
N/A
System Memory
System OS RAM
System OS Control
Internal USB port
USB interface via PCH. Accessed
via system OS
No write protect