Error Reference Guide

SR870BN4 Error Reference Guide Appendix A: Glossary
Revision 1.0
III
Term Definition
PEF Platform Event Filtering.
PEP Platform Event Paging.
PERR Parity Error. A signal on the PCI bus that indicates a parity error on the bus.
PID Programmable Interrupt Device. The PID is an interrupt controller that provides interrupt steering
functions. The PID interfaces include a PCI bus, an APIC bus, and serial IRQ interfaces, and an
interrupt input interface.
PIROM Processor Information ROM. SEEPROM contained in the processor module. Contains information
about the processor, such as the core ratio.
PLD Programmable Logic Device.
PMI Platform Management Interrupt.
POST Power-on Self Test.
RAM Random Access Memory.
RISC Reduced instruction set computing.
ROM Read-Only Memory.
RTC Real-Time Clock. Component of chipset on the baseboard.
SAL System Abstraction Layer.
SCI System Control Interrupt. A system interrupt used by hardware to notify the OS of ACPI events.
SDR Sensor Data Record.
SECC Single Edge Connector Cartridge.
SEEPROM Serial Electrically Erasable Programmable Read-Only Memory.
SEL System Event Log.
SERR System Error. A signal on the PCI bus that indicates a ‘fatal’ error on the bus.
SMBIOS System Management BIOS.
SMBus A two-wire interface based on the I2C protocol. The SMBus is a low-speed bus that provides
positive addressing for devices, as well as bus arbitration.
SMI Server Management Interrupt. SMI is the highest priority non-maskable interrupt.
SMM Server Management Mode.
SMS Server Management Software.
SNC Scalable Node Controller. The north bridge and memory controller (combined) in the 870 chipset.
SNMP
Simple Network Management Protocol.
UART
Universal Asynchronous Receiver/Transmitter.
UDP User Datagram Protocol.
USB Universal Serial Bus, a standard serial expansion bus meant for connecting peripherals.
Word 16-bit quantity.