Release Notes

BIOS Boot Selector for S5048F
Primary BIOS Version 3.38.0.1-4
SMF Version: MSS 1.4, FPGA 0.1
Last POR=0x11, Reset Cause=0x55
POST Configuration
CPU Signature 406D8
CPU FamilyID=6, Model=4D, SteppingId=8, Processor=0
Microcode Revision 125
Platform ID: 0x10041A56
PMG_CST_CFG_CTL: 0x40006
BBL_CR_CTL3: 0x7E2801FF
Misc EN: 0x840081
Gen PM Con1: 0x3008
Therm Status: 0x88350000
POST Control=0xEA000303, Status=0xE6009F00
BIOS initializations...
CPGC Memtest ................................ PASS
POST:
RTC Battery OK at last cold boot
RTC date 12/15/2020 13:39:09
POST SPD test ............................... PASS
POST Lower DRAM Memory test
.... Perf cnt (curr,fixed): 0x4F1A57C3C,0x9E34B3808
POST Lower DRAM Memory test ................. PASS
POST Lower DRAM ECC check ................... PASS
DxE POST
POST Upper DRAM Memory test
Short memory cell test
....
POST Upper DRAM Memory test ................. PASS
POST PCI test ............................... PASS
POST NVRAM check ............................ PASS
POST overall test results ................... PASS
NVRAM: 00 9F 00 E6 03 03 00 EA
Grub 2.02~beta2 (Dell EMC)
Built by root at gbbdev-maa-01 on Tue_Dec_15_08:55:22_UTC_2020
S5048F Boot Flash Label 3.38.2.6 NetBoot Label 3.38.2.6
Press Esc to stop autoboot ... 0
8. After the installation completes, the system displays the following DELL EMC prompt:
DellEMC>
Upgrading the CPLD
The S5048F-ON system with Dell EMC Networking OS Version 9.14(2.9) requires System complex programmable logic device
(CPLD) 1 revision 1, CPLD2 revision 1, CPLD3 revision 1, CPLD4 revision 1, MSS FPGA revision 0.1, MSS IAP revision 1.4, and
OOB-FPGA revision 1.0.
NOTE:
If your CPLD revisions are higher than the ones shown here, DO NOT make any changes. If you have questions
regarding the CPLD revision, contact Technical Support.
17