Reference Guide

Event Message Severity Cause
Err Reg Pointer OEM
Diagnostic data event was
asserted.
Information This event is generated when an OEM
event occurs. OEM events can be used
by the service team to better understand
the cause of the failure.
System Board PFault Fail Safe
state asserted.
Critical This event is generated when the system
board voltages are not at normal levels.
System Board PFault Fail Safe
state deasserted
Information This event is generated when earlier
PFault Fail Safe system voltages return to
a normal level.
Memory Add (BANK# DIMM#)
presence was asserted.
Information This event is generated when memory is
added to the system.
Memory Removed (BANK# DIMM#)
presence was asserted.
Information This event is generated when memory is
removed from the system.
Memory Cfg Err configuration
error (BANK# DIMM#) was
asserted.
Critical This event is generated when memory
configuration is incorrect for the system.
Mem Redun Gain redundancy
regained.
Information This event is generated when memory
redundancy is regained.
Mem ECC Warning transition to
non-critical from OK.
Warning This event is generated when correctable
ECC errors have increased from a normal
rate.
Mem ECC Warning transition to
critical from less severe.
Critical This event is generated when correctable
ECC errors reach a critical rate.
Mem CRC Err transition to
non-recoverable.
Critical This event is generated when CRC errors
enter a non-recoverable state.
Mem Fatal SB CRC
uncorrectable ECC was
asserted.
Critical This event is generated while storing CRC
errors to memory.
Mem Fatal NB CRC
uncorrectable ECC was
asserted.
Critical This event is generated while removing
CRC errors from memory.
Mem Overtemp critical over
temperature was asserted.
Critical This event is generated when system
memory reaches critical temperature.
USB Over-current transition
to non-recoverable
Critical This event is generated when the USB
exceeds a predefined current level.
Hdwr version err hardware
incompatibility (BMC/iDRAC
Firmware and CPU mismatch)
was asserted.
Critical This event is generated when there is a
mismatch between the BMC and iDRAC
firmware and the processor in use or vice
versa.
Hdwr version err hardware
incompatibility (BMC/iDRAC
Firmware and CPU mismatch)
was deasserted.
Information This event is generated when an earlier
mismatch between the BMC and iDRAC
firmware and the processor is corrected.
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