CLI Guide

Field Description
Processor Version Model and stepping number of the processor.
Current Speed Actual processor speed in MHz at system boot time.
State Whether the processor slot is enabled or disabled.
Core Count Number of processors integrated into one chip.
Capabilities and cache properties of a specic processor
To view the cache properties of a processor on a given connector, type:
omreport chassis processors index=n
or
omreport mainsystem processors index=n
The index parameter is optional. If you do not specify the index, Server Administrator displays properties for all processors. If you
specify the index, Server Administrator displays properties for a specic processor.
The following table lists the elds that are dened for the capabilities present on a particular microprocessor:
Table 24. Microprocessors and Fields
Microprocessor Fields
Intel Processor
• 64-bit Support
• Hyperthreading (HT)
• Virtualization Technology (VT)
• Demand-Based Switching (DBS)
• Execute Disable (XD)
• Turbo Mode
AMD Processor
• 64-bit Support
• AMD-V
• AMD PowerNow!
• No Execute (NX)
The following elds are dened for a cache present on a particular microprocessor. If the cache is internal to the processor, the elds
do not appear in the cache report:
• Speed
• Cache Device Supported Type
• Cache Device Current Type
• External Socket Name
The following table displays the elds that are displayed for each cache on a particular processor:
Table 25. Fields And Description
Field Description
Status Reports whether a specic cache on the processor is enabled or disabled.
Level Refers to a primary or secondary cache. Primary-level cache is a memory bank built into
the processor. Secondary-level cache is a staging area that feeds the primary cache. A
secondary-level cache is built into the processor or resides in a memory chipset outside the
processor. The internal processor cache is referred to as a Level 1 (or L1). L2 cache is the
external cache in a system with an Intel Pentium processor, and it is the second level of
cache that is accessed. The names L1 and L2 are not indicative of where the cache is
physically located (internal or external), but describe which cache is accessed rst (L1,
therefore internal).
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