Command Line Interface Guide

Microprocessor Fields

• Execute Disable (XD)

• Turbo Mode

AMD Processor

• 64-bit Support

• AMD-V

• AMD PowerNow!

• No Execute (NX)

The following fields are defined for a cache present on a particular microprocessor. If the cache is internal to the

processor, the fields do not appear in the cache report:

• Speed

• Cache Device Supported Type

• Cache Device Current Type

• External Socket Name

NOTE: Due to the limitations of certain operating systems (for example, VMware ESXi), certain features are not

available with this release of OpenManage Server Administrator.

The following table displays the fields that are displayed for each cache on a particular processor:

Table 10. Fields And Description

Field Description

Status Reports whether a specific cache on the processor is enabled or disabled.

Level Refers to a primary or secondary cache. Primary-level cache is a memory bank

built into the processor. Secondary-level cache is a staging area that feeds the

primary cache. A secondary-level cache is built into the processor or resides in a

memory chipset outside the processor. The internal processor cache is referred to

as a Level 1 (or L1). L2 cache is the external cache in a system with an Intel

Pentium processor, and it is the second level of cache that is accessed. The

names L1 and L2 are not indicative of where the cache is physically located

(internal or external), but describe which cache is accessed first (L1, therefore

internal).

Speed Refers to the rate at which the cache can forward data from the main memory to

the processor.

Max Size Maximum amount of memory that the cache can hold in kilobytes.

Installed Size Actual size of the cache.

Type Indicates whether the cache is primary or secondary.

Location Location of the cache on the processor or on a chipset outside the processor.

Write Policy

Describes how the cache deals with a write cycle. In a write-back policy, the

cache acts like a buffer. When the processor starts a write cycle, the cache

receives the data and stops the cycle. The cache then writes the data back to the

main memory when the system bus is available.