User's Manual

106 omconfig: Managing Components Using the Instrumentation Service
Mirror mode switches to a redundant copy of memory when an uncorrectable
memory event is detected. After switching to the mirrored memory, the
system does not switch back to the original system memory until the next
reboot. The operating system does not recognize half of the installed system
memory in this mode.
RAID mode provides an extra level of memory checking and error recovery at
the expense of some memory capacity.
Table 4-9 shows the valid parameters for the command.
Table 4-9. omconfig chassis memorymode/omconfig mainsystem memorymode
name=value pair 1 Description
index=<n> Number of the chassis where the memory module resides (the
default is chassis 0, the main system chassis).
redundancy=spare
| mirror | disabled
| raid5
Spare disables the memory module that has a correctable
memory event and copies the failing module’s data to a spare
bank.
Disabled indicates that the system is not to use other available
memory modules if uncorrectable memory events are detected.
Mirror switches the systems to a mirrored copy of the memory if
the failing module has an uncorrectable memory event. In the
mirror mode, the operating system does not switch back to the
original module until the system reboots.
RAID-5 is a method of system memory configuration. This is
logically similar to the RAID-5 mode used in hard drive storage
systems. This memory mode provides an extra level of memory
checking and error recovery at the expense of some memory
capacity. The RAID mode supported is RAID level 5 striping with
rotational parity.
opmode=mirror |
optimizer | advecc
Mirror switches the systems to a mirrored copy of the memory if
the failing module has an uncorrectable memory event. In the
mirror mode, the operating system does not switch back to the
original module until the system reboots.
Optimizer enables the DRAM controllers to operate
independently in 64-bit mode and provide optimized memory
performance.
Advanced ECC (advecc) enables the two DRAM controllers to
combine in 128-bit mode and provide optimized reliability.
Memory that cannot be teamed by the controllers is not reported
to the operating system.