User's Manual

36 omreport: Viewing System Status Using the Instrumentation Service
Fields Reported for Each Cache on a Particular Processor
Status reports whether a specific cache on the processor is enabled or disabled.
Level refers to primary or secondary cache. Primary-level cache is a memory bank built into the processor.
Secondary-level cache is a staging area that feeds the primary cache. A secondary-level cache may be built
into the processor or reside in a memory chip set outside the processor. The internal processor cache is
referred to as a Level 1 (or L1). L2 cache is the external cache in a system with an Intel Pentium
processor, and it is the second level of cache that is accessed. The names L1 and L2 are not indicative of
where the cache is physically located (internal or external), but describe which cache is accessed first
(L1, therefore internal).
Speed refers to the rate that the cache can forward data from main memory to the processor.
Max Size is the maximum amount of memory that the cache can hold in KB.
Installed Size is the actual size of the cache.
Ty p e indicates whether the cache is primary or secondary.
Location is the location of the cache on the processor or on a chip set outside the processor.
A Write Policy describes how the cache deals with a write cycle. In a write-back policy, the cache acts like
a buffer. When the processor starts a write cycle the cache receives the data and stops the cycle.
The cache then writes the data back to main memory when the system bus is available.
In a write-through policy, the processor writes through the cache to main memory. The write cycle does
not complete until the data is stored into main memory.
Associativity refers to the way main memory content is stored on the cache.
• A fully associative cache allows any line in main memory to be stored at any location in the cache.
• A 4-way set-associative cache directly maps four specific lines of memory to the same four lines of cache.
• A 3-way set-associative cache directly maps three specific lines of memory to the same three lines of cache.
• A 2-way set-associative cache directly maps two specific lines of memory to the same two lines of cache.
• A 1-way set-associative cache directly maps a specific line of memory in the same line of cache.
For example, line 0 of any page in memory must be stored in line 0 of cache memory.
Cache Device Supported Type is the type of static random access memory (SRAM) that the device
can support.
Cache Device Current Type is the type of the currently installed SRAM that the cache is supporting.
External Socket Name Silk Screen Name is the name printed on the system board next to the socket.
Error Correction Type identifies the type of error checking and correction (ECC) that this memory can
perform. Examples are correctable ECC or uncorrectable ECC.
This report shows cache information for each cache present on the microprocessor.