User's Manual
racadm racdump
Description
The racdump subcommand provides a single command to get dump, status, and general DRAC 4 board information.
The following commands are executed as a result of the single racdump subcommand:
l getsysinfo
l coredump
l memmap
l netstat
l getssninfo
Output
The output of the individual commands are displayed.
racreset
TableA-20 describes the racreset subcommand.
Table A-20. racreset
Synopsis
racadm racreset [hard | soft | graceful] [delay in seconds]
Description
The racreset subcommand issues a reset to the DRAC 4. The user is allowed to select how many seconds of delay occur before the reset sequence is started.
The reset event is written into the DRAC 4 log.
The default option is soft. If you do not type an option, the racadm CLI waits three seconds and then runs the soft option with the racreset subcommand.
TableA-21 describes the racreset subcommand options.
Table A-21. racreset Subcommand Options
Examples
NOTE: To use this command, you must have Configure DRAC 4 permission.
Subcommand
Definition
racreset
Resets the DRAC 4.
NOTICE: YoumustwaituntiltheDRAC4resetiscompletedbeforeissuinganothercommand.IftheDRAC4resetisnotcompleted,youmayreceivethe
following error: racadm <command name> Transport: ERROR: (RC=-1)
NOTICE: You must reboot your system after performing a hard reset of the DRAC 4 as described in the TableA-21.
Option
Description
hard
A hard reset resets the entire DRAC 4 and is as close to a power-on reset as can be achieved using software. The DRAC 4 log, database, and
selected daemons are shut down gracefully prior to the reset. A hard reset should be considered as a final effort. PCI configuration is lost.
soft
A soft reset is a processor and processor subsystem reset that resets the processor core to restart the software. PCI configurations are
preserved. The DRAC 4 log, database, and selected daemons are shut down gracefully prior to the reset.
graceful
A graceful reset is the same as a soft reset.
<delay>
The user is allowed to select how many seconds of delay occur before the reset sequence is started. A valid delay entry is between 1-60 seconds.
The default is 3 seconds.