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5 Real Time Streaming Analytics with Megh Computing on Dell EMC PowerEdge Servers
Figure 2. Examples of mission-critical applications require deterministic, fast response.
Intel Programmable Acceleration Card
The Intel Programmable Accelerator Card (PAC) features an Intel Arria 10 FPGA, an industry-leading
programmable logic built on 20 nm process technology, integrating a rich feature set of embedded
peripherals, embedded high-speed transceivers, hard memory controllers and IP protocol controllers.
Variable-precision digital signal processing (DSP) blocks integrated with hardened floating point (IEEE
754-compliant) enable Intel Arria 10 FPGAs to deliver floating point performance of up to 1.5 TFLOPS.
Arria 10 FPGAs have a comprehensive set of power-saving features. Combined, these features allow
developers to build a versatile set of acceleration solutions.
Figure 3. Intel Programmable Acceleration card. Figure 4. PAC Block Diagram.
Acceleration Stack
The Acceleration Stack for Intel Xeon CPU with FPGAs is a robust collection of software, firmware, and
tools designed and distributed by Intel to make it easier to develop and deploy Intel FPGAs for workload
optimization in the data center. The Acceleration Stack for Intel Xeon CPU with FPGAs provides multiple
benefits to design engineers, such as saving time, enabling code-reuse, and enabling the first common
developer interface.
Autonomous Vehicle
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