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Whitepaper – Balanced Memory with 2nd Generation Intel® Xeon Scalable Processors
© 2019 Dell Inc. or its subsidiaries.
Internal Use - Confidential
2. Memory Topography and Terminology
Figure 1: PowerEdge R740 CPU-to-memory subsystem connectivity for Intel® Cascade Lake™
To understand the relationship between the CPU and memory, terminology illustrated in
Figure 1 must first be defined:
• The memory controllers are digital circuits that manage the flow of data going from
the computer’s main memory to the corresponding memory channels.
2
Intel®
Xeon™ scalable processors have the controller integrated into the CPU.
• The memory channels control reading and writing bandwidth operations between
the CPU and memory modules.
3
Intel® Xeon™ scalable processors have six
memory channels, labeled one to six, which allow for increased data transfer rates
compared to previous generations.
• The memory slots host individual memory modules, such as DIMMs or DCPMMs.
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Intel® Xeon™ scalable processors have two slots per channel, shown as columns
A and B, so there are a total of twelve slots per CPU for memory module population.
• The memory subsystem is the combination of all the independent memory functions
listed above.