Reference Guide

14 Statement of Volatility – Dell DR6300, DR4300, DR4300e
Item
How is data input to this
memory?
How is this memory
write protected?
How is the memory cleared?
PCIe SSD Extension Card
Switch
Configuration
EEPROM
The EEPROM image is pre-
loaded at factory before
assembly. Once
assembled on the card,
data can be entered via
PLX Device Editor or PLX
EEP DOS based tool.
Device can be write
protected via
hardware pin.
Alternatively, device
contents can be write
protected via WPEN
bit in status register.
System is not functional as intended if
corrupted/removed.
IDSDM
SPI Flash
SPI interface via iDRAC
Hardware strapping
Not user clearable
MCU
USB3.0 interface via PCH,
FW can be updated via
iDRAC which runs on
Linux
N/A
Not user clearable
Left Ear - R730xd
SPI Flash
SPI interface via iDRAC
Hardware strapping
Not user clearable
Main Control Panel - R730
SPI Flash
SPI interface via iDRAC
Hardware strapping
Not user clearable
TPM
Trusted Platform
Module (TPM)
Using TPM Enabled
operating systems
SW write protected
F2 Setup option
iDRAC Quick Sync
MCU MSP430
I2C interface via iDRAC
Hardware strapping
Not user clearable - It also auto-clears
when power is applied.