Datasheet

Document ID Number: 328209 003EN Intel
®
Xeon Phi™ Coprocessor Datasheet
11
Note: Figure 2-2 and 2-3 are representative of the final Intel
®
Xeon Phi™ Coprocessor board
without the package thermal and mechanical solution.
2.1.2 System Management Controller (SMC)
The SMC has three I2C interfaces. This allows the SMC to have direct connection to the
coprocessor I2C interface, an on-board I2C sensor bus and a third interface through
the SMBus pins of the PCI Express* connector to the system management solution. The
I2C interface between the SMC and coprocessor is used for polling coprocessor thermal
status information. The sensor bus allows board thermal, input power, and current
Figure 2-2. Intel® Xeon Phi™ Coprocessor Board Top side (for reference only)
Figure 2-3. Intel® Xeon Phi™ Coprocessor Board, Back side (reference only)
GDDR
SystemManagement
Controller
Flash