Intel® Xeon Phi™ Coprocessor Datasheet April 2014 Document ID Number: 328209 003EN
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Table of Contents 1 Introduction .............................................................................................................. 7 1.1 Reference Documentation..................................................................................... 7 1.2 Conventions and Terminology ............................................................................... 7 1.2.1 Terminology ............................................................................................
List of Figures 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 6-1 6-1 6-2 Intel® Xeon Phi™ Coprocessor Board Schematic..................................................... 9 Intel® Xeon Phi™ Coprocessor Board Top side (for reference only) ..........................11 Intel® Xeon Phi™ Coprocessor Board, Back side (reference only).............................
List of Tables 1-1 1-2 2-1 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 Related Documents ............................................................................................. 7 General Terminology............................................................................................ 7 Intel® Xeon Phi™ Coprocessor Product Family ..................................................
Revision History Document Number Revision Number Description • • 328209 003 Updated product SKU Table 2-1. Added 31S1P, 7120A and 7120D. Added SKUs 31S1P and 7120A to relevant figures, paragraphs and tables throughout document. Added thermal throttling due to hot to VRs, Section 3.4.1.1. Minor changes and clarifications in power management and manageability chapter. April 2014 June 2013 • Updated product SKU Table 2-1. Updated mechanical specification Table 3-1 and thermal specification Table 3-2.
1 Introduction 1.1 Reference Documentation Table 1-1 lists most of the applicable documents. For complete list of documentation, contact your local Intel representative or go to www.intel.com. Table 1-1.
Table 1-2.
2.1 Intel® Xeon Phi™ Coprocessor Product Overview Figure 2-1.
• PCI Express* connections. • The clock system is integrated in the coprocessor including an on-board 100MHz +/ - 50ppm reference clock, and requires only the PCI Express* 100MHz reference clock input from the motherboard. The Intel® Xeon Phi™ coprocessor provides the following high-level features: • A many-core coprocessor. • Maximum 16-channel GDDR memory interface with an option to enable ECC. • PCI Express* 2.0 x16 interface with optional SMBus management interface.
Figure 2-2. Intel® Xeon Phi™ Coprocessor Board Top side (for reference only) Intel® Xeon Phi™ Coprocessor Silicon Outlet thermal sensor 150W 2x4 power connector Inlet thermal sensor 75W 2x3 power connector GDDR thermal sensor Blue Status LED Figure 2-3.
sense monitoring for system fan and power control. This information is forwarded to the coprocessor for power state control. The SMBus interface can be used by system for chassis fan control with the passive heat sink card and for integration with the Node Management controller in the platform. Communication with the system baseboard management controller (BMC) or peripheral control hub (PCH) occurs over the SMBus using the standard IPMB protocol. See chapter on manageability for more details. 2.1.
2.1.4 Intel® Xeon Phi™ Coprocessor Product Family Table 2-1. Intel® Xeon Phi™ Coprocessor Product Family SKU Card TDP (Watts) Cooling Solution1 3120A 300 Active 3120P / 7120P / SE10P 300 Passive2,4 7120X / SE10X 300 None2,3,4 31S1P 270 Passive 7120A 270 Active 7120D 270 None6 5120D 245 None5 6 225 Passive 5110P Notes: 1. Passive cooling solution uses topside heatsink (vapor chamber and copper fins) and backside aluminum plate. Active cooling uses on-card dual-intake blower. 2.
Figure 2-5.
3 Thermal and Mechanical Specification 3.1 Mechanical Specifications The mechanical features of the Intel® Xeon Phi™ coprocessor are compliant with the PCI Express* 225W/300W High Power Card Electromechanical Specification 1.0. Table 3-1 shows the mechanical specifications of Intel® Xeon Phi™ coprocessor passive and active SKUs. Table 3-1. Intel® Xeon Phi™ Coprocessor Mechanical Specification Parameter Specification Product Length 247.9mm1 Primary Side Height Keep-in 34.
Figure 3-1 Location of Mounting Holes on the Intel® Xeon Phi™ Coprocessor Card (in mils) Intel® Xeon Phi™ Coprocessor Datasheet 16 Document ID Number: 328209 003EN
Figure 3-2 Dimensions of the Intel® Xeon Phi™ Coprocessor Card (in mils) Document ID Number: 328209 003EN Intel® Xeon Phi™ Coprocessor Datasheet 17
3.2 Intel® Xeon Phi™ Coprocessor Thermal Specification Table 3-2. Intel® Xeon Phi™ Coprocessor Thermal Specification Parameter Specification TRISE 10°C Max TINLET 45°C Max TEXHAUST 70°C Tcase (processor) min, max 5°C, 95°C Tcontrol ~82°C1 Tthrottle 104°C2 Tthermtrip ~(Tthrottle + 20°C)3 Notes: 1. Tcontrol is the setpoint at which the system fans must ramp up towards full power (or RPM) to maintain the Intel® Xeon Phi™ coprocessor temperature around Tcontrol and prevent throttling.
Within 50ns of detecting Tthrottle, the DTS circuit begins stepping down the P-states until Pn is reached. Each frequency step is approximately 100MHz; the exact value will depend on the starting frequency. After each step, the DTS will wait 10uS before taking the next step. The number of steps, or P-states, depends on the starting frequency and the minimum frequency supported by the processor.
3.3.1 3120A and 7120A Active Cooling Solution For the 3120A and 7120A SKUs, the Intel® Xeon Phi™ coprocessor thermal-mechanical solution utilizes a supersink approach in which a primary heatsink is used to cool the coprocessor while a metallic fuselage/supersink cools the VR and GDDR components. Figure 3-4 illustrates the key components of the active cooling design.
3.3.2 7120P/SE10P/5110P/3120P/31S1P Passive Cooling Solution For the passive heat sink on the 7120P/SE10P/5110P/3120P/31S1P SKUs, the Intel® Xeon Phi™ coprocessor thermal & mechanical solution also utilizes a 'fuselage/ supersink' approach. Figure 3-5 illustrates the key components of the passive design. Figure 3-5 Exploded View of Passive Thermal Solution As in the active thermal solution, the duct is metallic and performs both structural and thermal roles.
If the system is able to provide a temperature lower than 45oC at the card inlet, then the total airflow can be reduced according to the graph and table in Figure 3-6. If the 5110P SKU is powered by a 2x4 and a 2x3 connector, the card can support an additional 20W of power for maximum TDP of 245W (see Section 2.1.5 for more details). In this case, the corresponding airflow requirement for cooling the part as a 245W card is shown in Figure 3-8. 3.3.2.
Figure 3-6 Airflow Requirement vs. 45oC Inlet Temperature for the 5110P at 225W TDP o Card Inlet ( C) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Document ID Number: 328209 003EN Total Flow (ft^3/min) Primary (ft^3/min) Secondary (ft^3/min) 10.6 10.8 11 11.2 11.4 11.6 11.8 12 12.2 12.5 12.7 13 13.3 13.6 13.9 14.2 14.6 15 15.4 15.8 16.2 16.7 17.2 17.8 18.4 19.1 7 7.1 7.3 7.5 7.7 7.9 8.1 8.3 8.5 8.7 9 9.2 9.5 9.8 10.1 10.4 10.7 11.1 11.4 11.8 12.2 12.7 13.1 13.6 14.
Figure 3-7 Airflow Requirement vs. Inlet Temperature for the 31S1P at 270W TDP and SE10P/7120P/3120P at 300W TDP o Card Inlet ( C) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Total Flow (ft^3/min) Primary (ft^3/min) Secondary (ft^3/min) Card dP (inH2 O) 14.4 14.7 15 15.3 15.6 16 16.3 16.7 17.1 17.6 18 18.5 19.1 19.7 20.3 21 21.7 22.5 23.3 24.3 25.3 26.5 27.8 29.2 30.9 32.8 10.5 10.8 11.1 11.3 11.7 12 12.3 12.7 13 13.4 13.8 14.3 14.8 15.3 15.8 16.4 17 17.6 18.4 19.
Figure 3-8 Airflow Requirement vs. Inlet Temperature for the 5110P Card at 245W TDP1 o Card Inlet ( C) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Total Flow (ft^3/min) Primary (ft^3/min) Secondary (ft^3/min) Card dP (inH2 O) 12.8 13 13.2 13.5 13.7 14 14.3 14.6 14.9 15.2 15.6 15.9 16.3 16.7 17.2 17.6 18.1 18.7 19.2 19.9 20.5 21.2 22 22.9 23.8 24.9 9.9 10 10.2 10.4 10.6 10.8 11 11.3 11.5 11.8 12 12.3 12.6 13 13.3 13.7 14.1 14.5 14.9 15.4 15.9 16.5 17.1 17.8 18.5 19.
3.4 Cooling Solution Guidelines for SE10X/7120X and 7120D/5120D The Intel® Xeon Phi™ coprocessor SE10X/7120X and 7120D/5120D SKUs are shipped without a thermal solution, which gives system designers and integrators an opportunity to fit these SKUs into their custom designed chassis. These SKUs have GDDR components on the back side that must be cooled, in addition to the front side where the coprocessor resides.
Figure 3-10 SE10X/7120X Power Profile for Memory Intensive Workload (all values in Watts) 1.9 1.7 0.4 1.7 0.4 1.7 0.4 1.7 0.4 1.4 0.3 2.3 0.6 1.9 1.9 1.9 1.9 1.9 187 1.9 0.4 1.7 0.4 1.7 0.4 1.7 1.9 0.4 1.7 0.3 1.4 0.6 2.3 1.9 1.9 1.9 1.9 1.9 1.9 0.3 1.4 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 Document ID Number: 328209 003EN 1.9 1.
Figure 3-11 5120D Power Profile: Coprocessor Centric (all values in Watts) VR FET 1.0 1.0 1.0 1.7 1.7 1.7 1.7 1.7 1.7 1.7 0.2 0.2 0.2 0.4 0.4 0.4 0.4 0.4 0.4 0.4 1.3 Topside 1.3 1.3 1.3 1.3 1.3 151 1.3 1.3 1.3 1.3 1.3 1.3 1.3 0.5 2.3 0.5 2.3 Backside 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 Intel® Xeon Phi™ Coprocessor 1.3 1.3 1.3 GDDR 1.3 1.3 1.3 Intel® Xeon Phi™ Coprocessor Datasheet 28 VR Inductor 1.3 GDDR 1.
Figure 3-12 5120D Power Profile: Memory Centric (all values in Watts) 1.1 1.1 1.1 1.7 1.7 1.7 1.7 0.3 0.3 0.3 0.4 0.4 0.4 0.4 0.4 0.4 0.4 1.7 1.7 1.7 1.9 1.9 1.9 1.9 1.9 1.9 141 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 0.5 2.1 0.5 2.1 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 Document ID Number: 328209 003EN 1.9 1.9 1.9 1.
Figure 3-13 7120D Power Profile: Coprocessor Centric (all values in Watts) VR FET 0.8 0.8 0.8 0.2 0.2 0.2 2.1 2.1 2.1 2.1 2.1 2.1 2.1 0.6 0.6 0.6 0.6 0.6 0.6 0.6 1.3 VR Inductor GDDR 1.3 1.3 1.3 1.3 1.3 198 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 0.8 3.2 0.8 3.2 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 Intel® Xeon Phi™ Coprocessor Datasheet 30 SMC 1.3 1.3 1.3 Intel Xeon Phi coprocessor silicon 1.3 1.3 1.3 1.
Figure 3-14 7120D Power Profile: Memory Centric (all values in Watts) 1.0 1.0 1.0 0.2 0.2 0.2 2.1 2.1 2.1 2.1 2.1 2.1 2.1 0.6 0.6 0.6 0.6 0.6 0.6 0.6 1.9 1.9 1.9 1.9 1.9 1.9 188 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 3.2 0.8 3.2 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 Document ID Number: 328209 003EN 0.8 1.9 1.9 1.
Table 3-3 shows thermal specifications of components present on the SE10X/7120X and 7120D/5120D boards. Table 3-3. Component Thermal Specification on SE10X/7120X and 7120D/5120D Component Thermal specification Coprocessor ≤ 95°C Tcase ≤ 85°C Tjunction ≤ 150°C1 Tbody ≤ 100°C Tcase GDDR VR FET VR Inductor Notes: ® 1.
3.4.2 Thermal Profile and Cooling The simplest cooling mechanism would involve running fans at full speed. For those custom air-cooled solutions that intend to be economical in fan power usage and acoustics, Figure 3-16 represents three regions on the SE10X/7120X coprocessor power consumption curve relevant to system fan control. Figure 3-16 SE10X/7120X SKU Coprocessor Junction Temperature (Tjunction) vs Power Tjunction 105.0 A 104°C 95.0 85.0 B C Temperature (oC) 75.0 D 65.0 55.0 45.
Figure 3-17 SE10X/7120X SKU Coprocessor Case Temperature (Tcase) vs Power Tcase 105.0 95.0 A <95°C 85.0 C Temperature (oC) 75.0 B D 65.0 55.0 45.0 0 50 100 150 200 Intel® Xeon Phi™ Coprocessor Si Power (W) For the region A-B, the cooling solution must maintain the case temperature below 95°C which will in turn maintain the coprocessor silicon junction temperature below 104°C.
3.4.3 Mechanical Considerations • In the passive Intel® Xeon Phi™ coprocessor products, the only component on the card with IHS load is the coprocessor. The compressive load is assumed to be approximately uniformly distributed over the IHS. The minimum load is 23lbf and maximum load is 75lbf. The mean pressure on the IHS is 33lbf. • Hitachi Type7 is recommended as the thermal interface material (TIM). • The gap filler used is the Bergquist 3500S35.
Figure 3-18 SE10X/7120X Board Top Side DRMOS VR Top‐side capacitor Inductor GDDR Co‐processor Memory VR Intel® Xeon Phi™ Coprocessor Datasheet 36 Core VR Document ID Number: 328209 003EN
Figure 3-19 SE10X/7120X Board Bottom Side Bottom‐side capacitor Document ID Number: 328209 003EN Intel® Xeon Phi™ Coprocessor Datasheet 37
Figure 3-20 7120D/5120D Board Top Side DRMOS VR Coprocessor VR Inductor Topside Capacitor Memory VR GDDR Coprocessor Intel® Xeon Phi™ Coprocessor Datasheet 38 Document ID Number: 328209 003EN
Figure 3-21 7120D/5120D Board Bottom Side Bottom‐side capacitors 3.4.4 Mechanical Shock and Vibration Testing Table 3-5 shows the recommended shock and vibration guidelines, and dynamic load shift specifications. Table 3-5. Dynamic Load Shift Specification Test Board Unpackaged Shock Specification and Guidelines 50g trapezoidal; V:170in/s drops: 3x each on 6 faces 5Hz @ 0.01g2/Hz to 20Hz @0.02g2/Hz (slope up) Board Unpackaged Random Vibration 20Hz to 500Hz @ 0.
Table 3-5. Dynamic Load Shift Specification Test Specification and Guidelines System Unpackaged Shock 25g trapezoidal; Varies by system weight (20-39lbs: 225 in/sec; 40-79lbs: 205 in/sec) drops: 2x each of 6 faces 5Hz @ 0.001g2/Hz to 20Hz @0.001g2/Hz (slope up) System Unpackaged Random Vibration 20Hz to 500Hz @ 0.001g2/Hz (flat) Input acceleration is 2.20g RMS 10mins per axis in all 3 axis 3.
3.5.1 Bracket Installation Steps 1. Determine Lid Type. If the lid type is “overlap” where the lid covers the top mounting holes as shown in Figure 3-23, then go to Step 2. If the lid type is “clearance” where the lid has cut-outs for mounting holes as shown in Figure 3-24, then go to Step 3.
2. Remove Overlap Lid. a. Remove 2 of the M3x6mm screws retaining the lid, as shown in Figure 3-25. Figure 3-25 Overlap Lid Removal b. Remove Lid. Take care not to bend tabs, as shown in Figure 3-26.
3. Install OEM Bracket. a. Insert the OEM bracket into the Intel® Xeon Phi™ coprocessor card assembly, as shown in Figure 3-27. Figure 3-27 OEM Bracket Installation “Overlap Lid” Units b. “Clearance Lid” Units Install (4) M3 x 6mm Flat Head Screws; torque = 6inch-lbs, shown in Figure 328. Figure 3-28 OEM Bracket Installation “Overlap Lid” Units “Clearance Lid” Units At this point, “clearance lid” units are ready to be mounted in the chassis.
4. Replace Lid on “Overlap Lid” Units Only a. Insert tabs into slots in card assembly, shown in Figure 3-29. Figure 3-29 Replace Lid on “Overlap Lid” Units Tabs inserted correctly b. Install the lid’s screws (M3 x 6mm Flat head); torque = 6 inch-lbs, shown in Figure 3-30. Figure 3-30 Replace Lid on “Overlap Lid” Units (cont.
4 Intel® Xeon Phi™ Coprocessor Pin Descriptions 4.1 PCI Express* Signals The PCI Express* connector for the Intel® Xeon Phi™ coprocessor is a x16 interface and supports signals defined in the “PCI Express* Card Electromechanical Specification”. Signals called out in the PCI Express* specification but not used on the Intel® Xeon Phi™ coprocessor are listed as “not used” in Table 4-1.
Table 4-1. PCI Express* Connector Signals on the Intel® Xeon Phi™ Coprocessor Signal Name 4.1.1 Signal Type Description SMB_PCI_CLK I/O PCI Express* System Management Bus Clock: SMB_PCI_CLK is the 3.3-volt clock signal for the SMBus Interface, which is normally used for power and/or thermal management and for monitoring the card. SMB_PCI_DAT I/O PCI Express* System Management Bus Data: SMB_PCI_DAT is the 3.
4.2 Supplemental Power Connector(s) The Intel® Xeon Phi™ coprocessor gets only maximum 75W from the PCI Express* connector, per the PCI Express* specification. The 2x4 and 2x3 supplemental power connectors on the coprocessor card provide the additional +12-volt power needed by the coprocessor. Per the PCI Express* specifications, the 2x4 connector must be capable of maximum 150W power draw by the coprocessor, and the 2x3 must be capable of maximum 75W power.
Table 4-2. 5120D (DFF) SKU Pinout Pin# Signal Type Pin# Signal Type B1 RSVD NC A1 PRSNT1_N GND B2 RSVD NC A2 RSVD NC B3 RSVD NC A3 RSVD NC B4 GND A4 GND B5 SMCLK O A5 RSVD NC B6 SMDAT I/O A6 RSVD NC B7 GND A7 RSVD NC B8 +3.3V A8 RSVD NC B9 RSVD A9 +3.3V B10 +3.3V_AUX A10 +3.
Table 4-2.
Table 4-2.
4.3.1 Baseboard Requirements of 5120D Unlike the Intel® Xeon Phi™ coprocessor PCI Express* card, the 5120D SKU requires the baseboard to implement input filter for the 12V and 3.3V power rails. There are no auxiliary or external power connectors on the 5120D and all power is supplied via the 230 pin edge connector. • Each 5120D product in the system requires a dedicated input filter for the +12V rail. • The filtering circuitry should be placed as close to the connector pins as possible. • The +3.
Intel® Xeon Phi™ Coprocessor Datasheet 52 Document ID Number: 328209 003EN
5 Power Specification and Management Power management on the Intel® Xeon Phi™ coprocessor is primarily managed via the on-board resident coprocessor OS with hardware-controlled functionality. Table 5-1 shows estimates for coprocessor power states and respective memory power states, along with estimates of corresponding card power and wakeup times. Table 5-1.
which will cause the frequency to drop to the minimum possible value (refer to Section 3.2.1). The level and duration of the power surge are programmable by the end user (refer chapter on manageability for more details). Additionally, there may be applications that draw up to 245W. This should be taken into account when choosing one of the three modes of operation as listed below: — Users can install both the 2x4 and 2x3 power connectors for total available power of 300W.
Figure 5-2. Some cores are in C0-state and other cores in C1-state; Memory in M0-state M0 M0 M0 C1 - Halt (clocks gated) M0 M0 M0 M0 M0 C0 (Full on) M0 M0 M0 VR Fan <100% M0 VR Full bandwidth enabled Coprocessor C1 state gates clocks on a core-by-core basis, reducing core power. On the active SKU, the fan slows to an appropriate speed, reducing fan power. If all cores enter C1, the coprocessor automatically enters Auto-pC3 state. Figure 5-3.
Figure 5-4. All Cores In Package-C3 State; Memory In M1 M1 M1 M1 M1 M1 Package C3 - Sleep (all core clocks gated) M1 M1 M1 M1 M1 VR M1 Fan ~20% VR M1 Full bandwidth enabled When all cores have entered C1 Halt state, the coprocessor package can reduce the core voltage and enter Deep-pC3. The fan (on active SKUs) can slow to minimum speed. VRs enter low power mode. Figure 5-5.
Figure 5-6. Package-C6 and Memory M2 state M2 M2 M2 M2 M2 Package C6 - Sleep (core power gating) M2 M2 M2 M2 M2 VR M2 Fan ~20% VR M2 Full bandwidth enabled The coprocessor OS can request that the coprocessor enter package C6 state. Core voltage is shut down. Coprocessor power is <10W1 in this state. Figure 5-7.
Each frequency setting of the coprocessor requires a specific voltage identification (VID) voltage setting in order to guarantee proper operation, and each P-state corresponds to one of these frequency and voltage pairs. Each device is uniquely calibrated and programmed at the factory with its appropriate frequency and voltage pairs. As a result, it is possible that two devices with the same frequency specification may have different voltage settings.
Figure 5-8.
Intel® Xeon Phi™ Coprocessor Datasheet 60 Document ID Number: 328209 003EN
6 Manageability 6.1 Intel® Xeon Phi™ Coprocessor Manageability Architecture The server management and control panel component of the Intel® Xeon Phi™ coprocessor architecture provides a system administrator with the runtime status of the Intel® Xeon Phi™ coprocessor installed in a given system. There are two access methods by which the server management and control panel component may obtain status information from the Intel® Xeon Phi™ coprocessor.
The manageability architecture also provides support for the Intel® Xeon Phi™ coprocessor in Node Manager mode, which adds functionality such as setting power throttle threshold values and time windows.
— P-state clamping if the P-state requested is not possible within the set power envelope • Power/energy measurement — Can choose to include or preclude 3.3V power 6.3 General SMC Features and Capabilities The Intel® Xeon Phi™ coprocessor supports the PCI Express* 2.0 standard. The SMC located on the card has direct access to information about the card operation (such as fan speeds, power usage, etc.) that must be managed from host-based software.
6.4 Host / In-Band Management Interface (SCIF) Manageability, through the SMC, is achievable via the SCIF interface which is part of the MPSS software stack. This allows host programs to obtain MIC telemetry and other information from the SMC managed features of the Intel® Xeon Phi™ coprocessor itself, as well as control SMC enabled functions. The SMC supports a host based SCIF interface.
The sensors available from the SMC vary within the Intel® Xeon Phi™ coprocessor family of products. However, the IPMI SDR sensor names will not change from release to release. Tinlet and Toutlet are derived numbers based on the Inlet and Outlet temperature sensors. The sensors located on the Intel® Xeon Phi™ coprocessor relate information about the CPU temperature as well as the temperature from three locations on the Intel® Xeon Phi™ coprocessor.
Note that the PL1, PL0 default thresholds are intended to be percentages of the TDP, and the SMC will dynamically determine actual values for the thresholds during coprocessor boot-up. No user intervention is necessary to enable power threshold throttling. System administrators may program PL1, PL0 thresholds and their respective time durations. The Software Development Kit (SDK) packaged in the coprocessor software stack, or MPSS (http://software.intel.
The SMC supports a read only IPMI SDR. It is hard-coded and not end-user updateable. The SDR can be read in “chunks”, suggested size is 16 bytes or the entire SDR can be read passing ‘FF’ as the number of bytes to read. 6.6.1 IPMB Protocol The IPMB protocol is a symmetrical byte-level transport for transferring IPMI messages between intelligent I2C devices. It is a worldwide standard widely used in the server management industry.
6.6.2.2 SMBus Write and Read Block Command Numbers 6.6.2.3 Write Description Table 6-1. SMBus Write Commands Command Figure 6-1.
6.6.2.4 Read Description Figure 6-2. Read Block Command Diagram 6.6.3 Supported IPMI Commands The SMC supports a subset of the standard IPMI sensor, SEL, and SDR commands along with several Intel OEM commands for accomplishing things like forcing throttle mode. The supported IPMI commands are documented in the following sections. Standard IPMI details are not documented in this document. For those please refer to the IPMI v2.0 specification.
6.6.3.3 SDR Related Commands Table 6-4. SDR Related Command Details NetFn Command Name Storage (0x0a) 0x20 Get SDR Repository Info Storage (0x0a) 0x21 Get SDR Repository Allocation Info Storage (0x0a) 0x23 Get SDR Note: The SDR can be read in “chunks”, suggested size is 16 bytes, or the entire SDR can be read by passing ‘FF’ as the number of bytes to read. 6.6.3.4 SEL Related Commands Table 6-5.
6.6.3.6 General Commands Table 6-7. General Command Details 6.6.3.6.1 NetFn Command Name Intel (0x2e) 0x42 CPU Package Config Read Intel (0x2e) 0x43 CPU Package Config Write Intel General App (0x30) 0x15 Set SM Signal CPU Package Configuration Read The CPU Package Config Read command reads power control data. For the parameter byte formats, refer to the Intel® XeonTM Processor Family External Design Specification (EDS) Volume 1. Table 6-8.
6.6.3.6.2 CPU Package Configuration Write The CPU Package Config Write command allows the setting of power control data. For the parameter byte formats, refer to the Intel Xeon Processor Family External Design Specification (EDS) Volume 1. Figure 2-36 in the EDS shows the format of the data word to effect writing the limits and the time windows. The index referenced below can be correlated to figure 2-36 as SMC-PL0 ==> RAPL-PL2 & SMC-PL1 ==> RAPL-PL1. Table 6-10.
Table 6-12. Set SM Signal Request Format (Continued) Byte # Value Description 1 0x00 • Instance 2 0x?? • • • • • Action If Signal is 1 1 - Assert: Start the identify blink code 2 - Revert: Return to normal operation All other values reserved [3] 0x00 • Value (optional) Table 6-13. Set SM Signal Response Format 6.6.3.
Table 6-16. Set Fan PWM Adder Command Response Format 6.6.3.7.2 Byte # Value 0 0x?? Description • • • Compcode 0x00 - Normal 0xc9 - Parameter out of range OEM Get POST Register The Get POST Register command allows the BMC to obtain the last POST code written to the SMC by the coprocessor. The SMC does not modify this value in any way. Table 6-17. Get POST Register Request Format Byte # Value Description Command 0x04 • OEM Get POST Register NetFn 0x3e • NETFN_OEM Table 6-18.
When the baseboard asserts PROCHOT (drives active low signal), the coprocessor OS immediately drops the frequency to lowest rated value (Pn) within 100µs of asserting PROCHOT. If PROCHOT is deasserted in less than 100ms, the coprocessor frequency is restored to the original operational value (either P1 or turbo).
The sensor names in the IPMI SDR are static and do not change from release to release. The IPMI sensor numbers are not static and may change between releases; hence the sensor number should be discovered during the normal sensor discovery process because additional sensors may be added in the future. During the normal sensor discovery process, reading the SDR returns the sensors available on the coprocessor. There is a sensor name and sensor number associated with each sensor.
Table 6-25. Table of Sensors Sensor Type fan_tach Sensor Description Fan tach read by SMC (N/A for passive SKUs, 5120D). OTHER status 6.6.3.9 Critical signal states (described in the datasheet).
6.7 SMC LED_ERROR and Fan PWM The SMC firmware drives the LED_ERROR pin as follows: Table 6-27. LED Indicators Blink Frequency 0.5HZ Blink Condition • In boot loader mode 2HZ Blink • Firmware update in progress 8HZ Blink • Operational code executing Identify Blink • • 2 short blinks every 2 seconds. Initiated by SetSMSignal command. The SMC drives the fan PWM to the static rate provided in the IPMI FRU while in boot loader mode.
