User guide

P5040 DS Hardware Getting Started, Rev. 1.5
Freescale Semiconductor 25
Switch Default Settings
SW11 Configuration:
SW11.1– SW11.4: PDN_CFG[0:3]
(Power Switches Configuration)
Defines PDN Power Switches control signals.
Details described in the Table Below.
• ‘0000’ - Independent; [Default for P5020]
• ‘0011’ - CA+CB - Common; PL - Independent; [Default for P5040]
• ‘0010’ - PL+CA+CB=Common; [Default for P3041]
• ‘0110’ - PL, CA - Independent; CB - Disconnected; [Default for P5021]
• ‘0101’ - PL+CA = Common; CB - Disconnected; [Default for P5010]
SW11.5: PROC_SEL2
(Processor Select)
Combined with SW4.7-SW4.6 defines processor type [2:0].
For detailes see description in SW4.6-SW4.7
• ‘0’ - Default for P3041/P5020
• ‘1’ - Default for P5040/P5021/P5010
SW11.6: LANE_9_SEL
Controls SerDes MUX routing of LANE_9_SEL:
• ‘1’ - AURORA [Default for P3041/P5020]
• ‘0’ - SLOT3 [Default for P5040]
SW11.7 – SW11.8: SDREFCLK4_FSEL[0:1]
(SerDes Reference Clock Bank4 Frequency Select)
Selects SerDes reference clock for P5040 bank4 [0:1] only;
not relevant for P3041/P5020.
• ‘00’ -100 MHz
• ‘01’ - 125 MHz [Default]
• ‘10’ - 156.25 MHz
• ‘11’ - 212.5 MHz;
8 7 6 5 4 3 2 1
SDREFCLK4_FSEL1 SDREFCLK4_FSEL0 LANE_9_SEL PROC_SEL2 PDN_CFG3 PDN_CFG2 PDN_CFG1
ON ’1’
PDN_CFG0
8 7 6 5 4 3 2 1
SDREFCLK4_FSEL1 SDREFCLK4_FSEL0 LANE_9_SEL PROC_SEL2 PDN_CFG3 PDN_CFG2 PDN_CFG1
ON ’1’
PDN_CFG0
For P3041/P5020:
For P5040:
SW11.1 SW11.2 SW11.3 PDN Config
000
000
001
001
010
010
011
011
Independent
PL+CA=Common; CB-Independant
PL+CA+CB=Common
CA+CB=Common; PL-Independant
Reserved
PL+CA=Common; CB-Disconnected
PL,CA=Independent; CB-Disconencted
Reserved
SW11.4
0
1
0
1
0
1
0
1
100
100
101
101
110
110
111
111
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PL-OFF; DUT not Powered