User guide

P5040 DS Hardware Getting Started, Rev. 1.5
2 Freescale Semiconductor
Revisions Table
1 Revisions Table
Table 1. Revisions Table
2 Acronyms and Abbreviations
Date Rev. Author Tech Editor Description
Dec 2011 1.0
Vladimir Yukht &
Limor Peretz
HWGS Rev. 1.0
Jan 2012 1.1
Vladimir Yukht &
Limor Peretz
HWGS Rev. 1.1
Jan 2012 1.2
Vladimir Yukht &
Limor Peretz
“Programming model” paragraph
removed (See User Guide for details)
March 2012 1.21
Vladimir Yukht &
Limor Peretz
P5021 device setting added
March 2012 1.22
Vladimir Yukht &
Limor Peretz
Photo’s are updated. Ref. clocks
default setting added
May 2012 1.3
Vladimir Yukht &
Limor Peretz
Default SYSCLK for P5040 changed to
100MHz
July 2012 1.4
Vladimir Yukht &
Limor Peretz
Default SYSCLK and PDN option for
P5040 changed to 133MHz & CA+CB
-Common; PL - Independent. P5021 &
P5010 devices setup added
Oct 2012 1.5
Vladimir Yukht &
Limor Peretz
Optional DDR_RST program control
added. FPGA OCM/DCM updated
Table 2.
Usage Description
ACK Acknowledge
ADDR Address
ARCH Architecture
ATX Advanced Technology Extended (power supply)
AURORA Aurora Systems
AUX Auxiliary
AVDD Address Bus Voltage
BRDCFG Board Configuration
BVDD Local Bus Direct Current Voltage