User guide

P5040 DS Hardware Getting Started, Rev. 1.5
Freescale Semiconductor 19
Switch Default Settings
SW5 Configuration
SW5.1 – SW5.2: SDREFCLK1_FSEL[0:1]
(SerDes Reference Clock Bank1 Frequency Select)
Selects SerDes reference clock for bank1[0:1].
• ‘00’ -100 MHz [Default]
• ‘01’ - 125 MHz
• ‘10’ - 156.25 MHz
• ‘11’ - 212.5 MHz; unsupported by P3041/P5020/P5040
SW5.3 – SW5.4: SDREFCLK2_FSEL[0:1]
(SerDes Reference Clock Bank2 Frequency Select)
Selects SerDes reference clock for bank2[0:1].
• ‘00’ - 100 MHz
• ‘01’ - 125 MHz [Default]
• ‘10’ - 156.25 MHz
• ‘11’ - 212.5 MHz; unsupported by P3041/P5020/P5040
SW5.5 – SW5.6: SDREFCLK3_FSEL[0:1]
(SerDes Reference Clock Bank3 Frequency Select)
Selects SERDES Reference Clock for Bank3[0:1].
• ‘00’ - 100 MHz
• ‘01’ - 125 MHz [Default]
• ‘10’ - 156.25 MHz
• ‘11’ - 212.5 MHz; unsupported by P3041/P5020/P5040
SW5.7 – SW5.8: UART1_3_SEL[0:1]
(UART Connection Select)
Controls UART1 and UART3 connectivity options[0:1].
• ‘00’ - UART1 is connected to RS-232 DB9 BOTTOM; Selects UART1 with flow
control if SW3.4: UART3_nUART1=’0’. [Default]
– Selects UART1 without flow control if SW3.4: UART3_nUART1=’1’.
• ‘01’ - UART3 or Reserved
– Connects UART3 to RS-232 DB9 BOTTOM if SW3.4: UART3_nUART1=’1’
– Reserved if SW3.4: UART3_nUART1=’0’.
• ‘10’ - Connects FPGA to RS-232 DB9 BOTTOM; the UART processor is not used.
• ‘11’ - Reserved
8 7 6 5 4 3 2 1
UART1_3_SEL1 UART1_3_SEL0 SDREFCLK3_FSEL1 SDREFCLK3_FSEL0 SDREFCLK2_FSEL1 SDREFCLK2_FSEL0 SDREFCLK1_FSEL1
ON ’1’
SDREFCLK1_FSEL0