User guide

P5040 DS Hardware Getting Started, Rev. 1.5
18 Freescale Semiconductor
Switch Default Settings
SW4 Configuration
SW4.1– SW4.2: GPINPUT[0:1]
(General Purpose Input)
Overwrites PLL settings when CFG_PLL_CONFIG_SEL_B = 1'b0.
• ‘11’ - Default
SW4.3 – SW4.4: SVR [0:1]
(System Version Register)
Defines system version register [0:1].
• ‘00’ - Reserved
• ‘01’ - Reserved
• ‘10’ - Reserved
• ‘11’ - P5040/P3041/P5020/P4080 [Default]
SW4.5: TESTSELb
(Test Select)
Defines functionality.
• ‘0’ - for P3041/P5021/P5010
• ’1’ - for P5040/P5020/P4080
SW4.6 – SW4.7: PROC_SEL[0:1]
(Processor Select)
Combined with SW11.5 defines processor type:
SW11.5, SW4.7 ,SW4.6, = Processor type[2:0].
For detailes see the Table below.
SW4.8: I
2
C1_PROC_ISO
(Processor Isolated)
Controls CPU access to I
2
C1 connected devices: I
2
C RCW EEPROM, SYSTEM
Configuration DATA EEPROM, DC-to-DC power supplies for CPU CA, CB, PL, and
GVDD voltages.
• 0 - CPU cannot access devices
• 1 - CPU accesses [Default]
NOTE!
If SW8.1 = ‘1’ then the CPU can access the EEPROM FPGA
ExConfiguration Data.
8 7 6 5 4 3 2 1
I
2
C1_PROC_ISO
PROC_SEL1 PROC_SEL0 TESTSELb SVR1 SVR0 GPINPUT1
ON ’1’
GPINPUT0
8 7 6 5 4 3 2 1
I
2
C1_PROC_ISO
PROC_SEL1 PROC_SEL0 TESTSELb SVR1 SVR0 GPINPUT1
ON ’1’
GPINPUT0
For P5040:
For P3041/P5020:
SW11.5 SW4.7 SW4.6 Processor Type
000
001
010
011
100
101
110
111
P4080
P3041
P5020
P2040
P5040
P5010
P5021
Reserved