User guide

P5040 DS Hardware Getting Started, Rev. 1.5
Freescale Semiconductor 17
Switch Default Settings
SW3 Configuration
SW3.1: SD1_CLKSPREAD
(SerDes Clock Spread)
Controls SERDES Bank1 clock spread spectrum modulation—determines if enabled
or disabled.
• ‘0’ - SD1_CLKSPREAD disabled [Default]
• ’1’ - Enabled SD1_CLKSPREAD
NOTE!
To use SERDES Bank1 spread spectrum modulation oscillator Y2 and
R216 & R217 should be assembled while R213 & R214 - are
disassembled.
SW3.2: UART2_nUART4
(Universal Asynchronous Receiver/Transmitter)
• ’1’ - P3041/P5020/P5040 UART2 connected to RS-232 DB9 TOP [Default]
• ‘0’ - P3041/P5020/P5040 UART4 connected to RS-232 DB9 TOP
SW3.3: UART2_UART4_SHDN
(UART_Shutdown)
• ‘0’ - Active UART2/UART4 connected to RS-232 DB9 TOP [Default]
• ’1’ - UART2/UART4 in shutdown mode
SW3.4: UART3_nUART1
(Universal Asynchronous Receiver/Transmitter)
Controls P3041/P5020/P5040 UART3/UART1 Flow Control—determines if
connected to RS-232 DB9 BOTTOM; see SW5.7 – SW5.8 description.
• ‘0’ - P3041/P5020/P5040 UART1 Flow Control (RTS, CTS) connected to
RS-232 DB9 BOTTOM [Default]
• ’1’ - P3041/P5020/P5040 UART3 connected to RS-232 DB9 BOTTOM.
SW3.5: XVDD_SEL
(Select XVDD Voltage)
Controls XVDD voltage.
• ‘0’ - XVDD = 1.8V [Default]
• ‘1’ - XVDD = 1.5V
SW3.6 – SW3.8: SYSCLK[0:2]
(System Clock Select)
Selects SYSCLK[0:2] speed as listed below:
• ‘000’ - 66.666 MHz
• ‘001’ - 83.333 MHz [Default for P3041]
• ‘010’ - 100 MHz
• ‘100’ - 133.333MHz [Default for P5040]
• ‘011’ - 125 MHz
• ‘100’ - 133.333 MHz [Default for P5020]
• ‘101’ - 150 MHz
• ‘110’ - 160 MHz
• ‘111’ - 166.666 MHz
8 7 6 5 4 3 2 1
SYSCLK2 SYSCLK1 SYSCLK0 XVDD_SEL UART3_nUART1 UART2_UART4_SHDN UART2_nUART4
ON ’1’
SD1_CLKSPREAD
For P3041:
For P5020:
8 7 6 5 4 3 2 1
SYSCLK2 SYSCLK1 SYSCLK0 XVDD_SEL UART3_nUART1 UART2_UART4_SHDN UART2_nUART4
ON ’1’
SD1_CLKSPREAD
For P5040:
8 7 6 5 4 3 2 1
SYSCLK2 SYSCLK1 SYSCLK0 XVDD_SEL UART3_nUART1 UART2_UART4_SHDN UART2_nUART4
ON ’1’
SD1_CLKSPREAD