User guide

P5040 DS Hardware Getting Started, Rev. 1.5
16 Freescale Semiconductor
Switch Default Settings
SW2 Configuration
SW2.1 – SW2.6: SerDes MUX Configuration
Controls SerDes MUX routing; see Hydra DS SERDES Support and P5040 DS
Serdes Support.
• LANE_23_SEL: Selects routing of LANES[2:3]:
‘0’ - SLOT4 [Default for P3041/P5020]
‘1’ - SLOT7 [Default for P5040]
• LANE_45_SEL: Selects routing of LANES[4:5] ‘0’ - SLOT6 [Default], ‘1’ - SLOT7
• LANE_67_SEL[0:1]: Selects routing of LANES[6:7]
– ‘00’ - SLOT5 [Default for P5040]
– ‘10’ - SLOT6 [Default for P3041/P5020]
–‘01’ - SLOT7
– ‘11’ - NA
• LANE_8_SEL: Selects routing of LANE[8]:
’0’ - AURORA [Default for P3041/P5020]
‘1’ - SLOT3 [Default for P5040]
• LANE_1617_SEL: Selects routing of LANES[16:17]:
‘0’ - SATA [Default for P3041/P5020]
‘1’ - SLOT1 [Default for P5040]
SW2.7: EP_nRC
(End Point_nRoot Complex)
Controls SLOT7—determines its use as a PEX RC or a PEX EP.
• ‘0’ - SLOT7 as an RC [Default]
• ’1’ - SLOT7 as an EP
SW2.8: ENG_USE3
(Engineering Use3)
[Future option] Defines functionality.
• ‘1’ - Default
• ’0’ - Spare
8 7 6 5 4 3 2 1
ENG_USE3 EP_nRC LANE_1617_SEL LANE_8_SEL LANE_67_SEL1 LANE_67_SEL0 LANE_45_SEL
ON ’1’
LANE_23_SEL