User guide

P5040 DS Hardware Getting Started, Rev. 1.5
12 Freescale Semiconductor
Switch Default Settings
6 Switch Default Settings
Default DIP-switch positions establish the P5040 DS (SuperHYDRA) mode; see Table 5.
NOTE!
Ensure DIP-switches are set according to default values.
Table 4. P5040 DS (SuperHYDRA) Default Configurations
Mode Term Default Value Unit
AVDD_CC1, AVDD_CC2,
AVDD_PLAT, AVDD_DDR
PLL’s Supply Voltages
(Core, Platform and DDR)
1.05 for P3041/P5020
1.0 for P5040
V
AVDD_SRDS1, AVDD_SRDS2,
AVDD_SRDS3
SERDES PLL’s Supply Voltages
(Filtered from SVDD)
1.05 for P3041/P5020
1.0 for P5040
V
BVDD Voltage eLBC Block Supply Voltage 3.3 only V
Core Clock Depends on RCW
2260 (P5040) /
2000 (P5020/P3041)
MHz
CVDD Voltage SPI & SDHC Blocks Supply Voltage 3.3 V
DDR CLK Depends on RCW
800 (P5040) /
666 (P5020/P3041)
MHz
Fman CLK Depends on RCW 600 MHz
GVDD Voltage DDR DRAM I/O Supply Voltage 1.5 V
LVDD Voltage Ethernet EMI1, 1588, GPIO Voltage 2.5 V
OVDD Voltage
DUART, I
2
C, DMA, MPIC, GPIO,
system control and power manage-
ment, clocking, debug, I/O voltage
select, and JTAG I/O voltage
3.3 V
Platform Clock Depends on RCW 800 MHz
POVDD Voltage
Fuse programming override supply
Voltage
“0”- Default
1.0/1.5
V
RTC CLK Real-time Clock ~50 KHz
SerDes REF CLK1 SerDes Reference Clock 1 100 MHz
SerDes REF CLK2 SerDes Reference Clock 2 125 MHz
SerDes REF CLK3 SerDes Reference Clock 3 125 MHz
SerDes REF CLK4 SerDes Reference Clock 4 125 (P5040 only) MHz
SVDD Voltage
Core power supply for SerDes
transceivers Voltage
1.05 for P3041/P5020
1.0 for P5040
V
SYSCLK (Synthesizer REF CLK) System Clock
133.333 (P5040/
P5020)/
83.333 (P3041)
MHz
USB_VDD_1P0 USB PHY PLL supply Voltage 1.0 V