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Freescale Semiconductor

Hardware Getting Started Guide

This document describes the P5040 DS (SuperHYDRA) and

its related hardware kit. The P5040 DS (SuperHYDRA)

Getting Started procedure explains and verifies basic board

operation in a step-by-step format.

Settings for switches, connectors, jumpers, push buttons, and

LEDs are shown, and there are instructions for connecting

peripheral devices.

The P5040 DS (SuperHYDRA) functions with an integrated

development environment (IDE), such as Freescale’s

CodeWarrior ™; however, instructions for working with the

IDE are beyond the scope of this document.

P5040 DS (SuperHYDRA)

Document Number: P5040 DS_HGS

Rev. 1.5

Contents

1. Revisions Table 2

2. Acronyms and Abbreviations 2

3. Related Reading 8

4. Hardware Kit Contents 9

5. P5040 DS (SuperHYDRA) Component and Print

Side Views 10

6. Switch Default Settings 12

7. Connector Default Settings 29

8. Jumper Default Settings 32

9. Push Buttons 33

10. LED Lights 34

11. Working Environment 37

12. HW Getting Started Procedures 37

12.1 Standalone Mode 38

12.2 PC Mid-Tower Mode 40

13. SerDes Options 42

Summary of content (44 pages)

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Freescale Semiconductor Hardware Getting Started Guide Document Number: P5040 DS_HGS Rev. 1.5 P5040 DS (SuperHYDRA) Contents This document describes the P5040 DS (SuperHYDRA) and its related hardware kit. The P5040 DS (SuperHYDRA) Getting Started procedure explains and verifies basic board operation in a step-by-step format. Settings for switches, connectors, jumpers, push buttons, and LEDs are shown, and there are instructions for connecting peripheral devices.
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Revisions Table 1 Revisions Table Table 1. Revisions Table Date Rev. Author Tech Editor Description Dec 2011 1.0 Vladimir Yukht & Limor Peretz HWGS Rev. 1.0 Jan 2012 1.1 Vladimir Yukht & Limor Peretz HWGS Rev. 1.1 Jan 2012 1.2 Vladimir Yukht & Limor Peretz “Programming model” paragraph removed (See User Guide for details) March 2012 1.21 Vladimir Yukht & Limor Peretz P5021 device setting added March 2012 1.22 Vladimir Yukht & Limor Peretz Photo’s are updated. Ref.
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Acronyms and Abbreviations Table 2.
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Acronyms and Abbreviations Table 2. Usage Description eSDHC Enhanced Secure Digital High Capacity Card esig Internal/Event Signal p.
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Acronyms and Abbreviations Table 2. Usage Description LED/LD Light-emitting Diode LP Low Power LSB Least Significant Bit LVDD P5040 DS (SuperHYDRA) GETH (Low) Voltage MII Media Independent Interface MMC Multi-media Card MSB Most Significant Bit MUX Multiplexer NAND Flash Memory NDA Non-Disclosure Agreement NG/ng New Generation; e.g.
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Acronyms and Abbreviations Table 2. Usage Description PS Power Supply PWR Power QorIQ Brand of power architecture based on a Freescale communications micro controller.
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Acronyms and Abbreviations Table 2. Usage Description SPI Serial Peripheral Interface Flash SPICS SPI Chip Select SRAM Static Random Access Memory STAT Status SVDD Supply Voltage SVR System Version SW Switch SXSLOT SGMII/XAUI Riser Card Slot SYSCLK System Clock TAP Telocator Alphanumeric Protocol; e.g.
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Related Reading 3 Related Reading The documents listed in the below table are available via the Freescale website to those with NDA access. The website is found at http://www.freescale.com/. Table 3. Related Reading Document Description CodeWarrior™ Kit Configuration Guide • Complete HW setup explanation. • Kit Configuration Guide explains how to set up and use each SW component in the development kit.
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Hardware Kit Contents 4 Hardware Kit Contents This section lists and depicts (see Figure 1) HW kit contents. Figure 1. HW Kit Contents HW Kit Inventory Photo A: Board and External HW 1. P5040 DS (SuperHYDRA) board (1) with connected DB9 Cross Gender adapter (1) 1 2. PC Mid-Tower 3. ATX PS 12V 600W (1) and US/Canada cable & PS adapter A 2 3 4. CodeWarrior USB TAP (1 kit) 5. DVD/CD: SATA2 (1) 6. HD: 160GB SATA (1) Photo B: Cables 7. ETH cross-over cable with RJ45 connector (1) 4 8.
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P5040 DS (SuperHYDRA) Component and Print Side Views 5 P5040 DS (SuperHYDRA) Component and Print Side Views Figure 2 shows the component side and Figure 3 shows the print side of P5040 DS (SuperHYDRA). Figure 2.
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P5040 DS (SuperHYDRA) Component and Print Side Views Figure 3.
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Switch Default Settings 6 Switch Default Settings Default DIP-switch positions establish the P5040 DS (SuperHYDRA) mode; see Table 5. NOTE! Ensure DIP-switches are set according to default values. Table 4. P5040 DS (SuperHYDRA) Default Configurations Mode Term Default Value Unit AVDD_CC1, AVDD_CC2, AVDD_PLAT, AVDD_DDR PLL’s Supply Voltages (Core, Platform and DDR) 1.05 for P3041/P5020 1.0 for P5040 V AVDD_SRDS1, AVDD_SRDS2, AVDD_SRDS3 SERDES PLL’s Supply Voltages (Filtered from SVDD) 1.
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Switch Default Settings Table 4. P5040 DS (SuperHYDRA) Default Configurations Mode Term Default Value Unit 3.3 V USB_VDD_3P3 USB PHY Transceiver supply Voltage VDD_CA Voltage Cores Group A supply voltage (not used for P3041) 1.1 for P5020/P5040 V VDD_CB Voltage Cores Group B supply voltage (not used for P3041) 1.1 for P5020/P5040 V VDD_LP Voltage Low Power Security Monitor Supply 1.0 V VDD_PL for P5020/P5040 VDD_PL_CA_CB for P3041 Voltage Platform/Combined Supply Voltage 1.
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Switch Default Settings Table 5 provides schematic drawings and related switch descriptions. Table 5. SW Configurations RCW_SRC0 RCW_SRC1 RCW_SRC2 RCW_SRC3 RCW_SRC4 DRAM_TYPE RSP_DIS eLBC_ECC SW1.1 – SW1.5: RCW_SRC[0:4] (RCW Configuration Source) Defines RCW configuration sources [0:4] as per P3041/P5020 RM. 1 2 3 4 5 6 7 8 ON ’1’ SW1 Configuration (Default) Defines RCW configuration sources [0:4] as per P5040 RM. Here should be the Table for P5040 P5040 DS Hardware Getting Started, Rev. 1.
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Switch Default Settings SW1.6: DRAM_TYPE (DDR RAM Type) Defines POR DRAM type (DDR3/DDR3L). • ‘0’ - 1.5V DDR3 technology [Default] • ’1’ - 1.35V DDR3L technology SW1.7: RSP_DIS (Response Disable) Defines functionality. • ‘0’ - RESET pauses at RCW • ’1’ - Continued Boot [Default] SW1.8: eLBC_ECC (Enhanced Local Bus Controller & Error Detection and Correction) Controls FCM ECC functionality. • ‘0’ - Disabled NAND Flash ECC [Default] • ’1’ - Enabled NAND Flash ECC P5040 DS Hardware Getting Started, Rev. 1.
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Switch Default Settings SW2 Configuration LANE_23_SEL LANE_45_SEL LANE_67_SEL0 LANE_67_SEL1 LANE_8_SEL LANE_1617_SEL EP_nRC ENG_USE3 1 2 3 4 5 6 7 8 ON ’1’ SW2.1 – SW2.6: SerDes MUX Configuration Controls SerDes MUX routing; see Hydra DS SERDES Support and P5040 DS Serdes Support.
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Switch Default Settings SW3 Configuration SW3.
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Switch Default Settings SW4 Configuration SW4.1– SW4.2: GPINPUT[0:1] (General Purpose Input) GPINPUT0 GPINPUT1 SVR0 SVR1 TESTSELb PROC_SEL0 PROC_SEL1 I2C1_PROC_ISO GPINPUT0 GPINPUT1 SVR0 SVR1 TESTSELb PROC_SEL0 PROC_SEL1 I2C1_PROC_ISO 1 2 3 4 5 6 7 8 ON ’1’ For P3041/P5020: SW4.3 – SW4.4: SVR [0:1] (System Version Register) Defines system version register [0:1]. • ‘00’ - Reserved • ‘01’ - Reserved • ‘10’ - Reserved • ‘11’ - P5040/P3041/P5020/P4080 [Default] SW4.
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Switch Default Settings SDREFCLK1_FSEL0 SDREFCLK1_FSEL1 SDREFCLK2_FSEL0 SDREFCLK2_FSEL1 SDREFCLK3_FSEL0 SDREFCLK3_FSEL1 UART1_3_SEL0 UART1_3_SEL1 ON ’1’ SW5 Configuration SW5.1 – SW5.2: SDREFCLK1_FSEL[0:1] (SerDes Reference Clock Bank1 Frequency Select) Selects SerDes reference clock for bank1[0:1]. • ‘00’ -100 MHz [Default] • ‘01’ - 125 MHz • ‘10’ - 156.25 MHz • ‘11’ - 212.5 MHz; unsupported by P3041/P5020/P5040 1 2 3 4 5 6 7 8 SW5.3 – SW5.
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Switch Default Settings SW6 Configuration RESERVED RESERVED RESERVED RESERVED VDD_CB0 VDD_CB1 VDD_CB_EN POVDD_PWR_EN 1 2 3 4 5 6 7 8 ON ’1’ SW6.1– SW6.4: RESERVED SW6.5 – SW6.6: VDD_CB[0:1] (Core B Voltage) [Optional] Defines additional core B voltage[0:1]. • ‘00’ - HW defined by switch SW10[3:4] [Default] • ‘01’ - Reserved (1.00V) • ‘10’ - 1.05V • ‘11’ - Reserved (1.15V) SW6.7: VDD_CB_EN (Core B Voltage Enabled) Controls Core B voltage—determines if enabled or disabled.
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Switch Default Settings LBMAP0 LBMAP1 LBMAP2 LBMAP3 ENG_USE0 ENG_USE1 ENG_USE2 RESET_REQ_BYPASS 1 2 3 4 5 6 7 8 ON ’1’ SW7 Configuration SW7.1 – SW7.4: LBMAP[0:3] (Local Bus Map) Controls local bus chip select options.
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Switch Default Settings SW8 Configuration I2C1_FORCE RCW_WP FLASH_WP ID_WP AURORA_CLK_EN POVDD_CNTL RESET_REQ_MODE JTAG_AURORA_SEL Controls CPU access to I2C1 connected devices owned by ngPIXIS device: FPGA as well as EEPROM FPGA Configuration Data and EEPROM ExConfiguration Data. • 0 - System cannot access devices • 1 - System can access devices [Default] NOTE! If SW4.8 = ‘1’ then the CPU accesses above noted devices. SW8.2: RCW_WP (RCW Write Protect) 1 2 3 4 5 6 7 8 ON ’1’ SW8.
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Switch Default Settings SW9 Configuration PIXISOPT0 PIXISOPT1 IPLWP CFGWP ATX-PS RESERVED CFGOPT0 CFGOPT1 ON ’1’ SW9.1 – SW9.2: PIXISOPT[0:1] (ngPIXIS Option) Controls OCM/DCM ngPIXIS options. • PIXISOPT[0] = ‘0’ - Enabled debugger • PIXISOPT[0] = ‘1’ - Disabled debugger [Default] • PIXISOPT[1] = unused; ‘1’ - [Default] 1 2 3 4 5 6 7 8 SW9.3: IPLWP (IPL Write Protect) Defines EEPROM FPGA ExConfiguration Data WP. • ‘0’ - No EEPROM WP • ’1’ - EEPROM WP [Default] SW9.
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Switch Default Settings SW10 Configuration: RESERVED RESERVED SW_ZL_CB_V_SEL_A1 SW_ZL_CB_V_SEL_A0 RESERVED RESERVED RESERVED RESERVED 1 2 3 4 5 6 7 8 ON ’1’ SW10.1– SW10.2: RESERVED SW10.3 – SW10.4: SW_ZL_CB_V_SEL_A[1:0] (Software Core B Voltage Select) Defines core B voltage. • ‘00’ - 1.0V; • ‘01’ - 1.1V; [Default] • ‘10’ - 1.2V • ‘11’ - 0.9V SW10.5 – SW10.8: RESERVED P5040 DS Hardware Getting Started, Rev. 1.
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Switch Default Settings SW11 Configuration: PDN_CFG0 PDN_CFG1 PDN_CFG2 PDN_CFG3 PROC_SEL2 LANE_9_SEL SDREFCLK4_FSEL0 SDREFCLK4_FSEL1 SW11.1– SW11.4: PDN_CFG[0:3] (Power Switches Configuration) PDN_CFG0 PDN_CFG1 PDN_CFG2 PDN_CFG3 PROC_SEL2 LANE_9_SEL SDREFCLK4_FSEL0 SDREFCLK4_FSEL1 1 2 3 4 5 6 7 8 ON ’1’ For P3041/P5020: SW11.1 SW11.2 SW11.3 SW11.
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Switch Default Settings SW12 Configuration: SW12_1 SW12_2 SW12_3 SW12_4 SW12_5 SW12_6 SW12_7 SW12_8 1 2 3 4 5 6 7 8 ON ’0’ SW12.1– SW12.8: VDD_CA_VOLT_SET (VDD_CA voltage set) Defines VR11 Intel Mode voltage identification codes for VDD_CA. See Intersil ISL6313B data sheet. SW12[1:8] = U135 ISL6313B[VID0:VID7] Details described in the Table Below. • ‘01001010’ - SW12[1:8], 1.10000V; [Default] SW12.8 SW12.7 SW12.6 SW12.5 SW12.4 SW12.3 SW12.2 SW12.
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Switch Default Settings SW13 Configuration: SW13.1– SW13.8: VDD_PL_VOLT_SET (VDD_PL voltage set) SW13_1 SW13_2 SW13_3 SW13_4 SW13_5 SW13_6 SW13_7 SW13_8 Defines VR11 Intel Mode voltage identification codes for VDD_PL. See Intersil ISL6313B data sheet. SW13[1:8] = U147 ISL6313B[VID0:VID7] Details described in the Table Below. • ‘01011010’ - SW13[1:8], 1.05000V; [Default for P5020] • ‘00011010’ - SW13[1:8], 1.06250V; [Default for P3041] • ‘10000110’ - SW13[1:8], 1.
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Switch Default Settings Figure 4 shows DIP-switch location. Figure 4. P5040 DS (SuperHYDRA) DIP-Switch Locations SW12 SW13 SW1 SW9 SW5 SW2 SW10 SW6 SW3 SW7 SW11 SW4 SW8 P5040 DS Hardware Getting Started, Rev. 1.
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Connector Default Settings 7 Connector Default Settings Table 6 lists factory default connector settings for P5040 DS (SuperHYDRA). Figure 5 notes connector locations. Table 6.
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Connector Default Settings Table 6.
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Connector Default Settings Table 6. P5040 DS (SuperHYDRA) Connector Default Settings Connector Name/Function P1 Type Features Description GETH2 RJ-45 12-pin [Default] OPEN U52 NAND Flash socket Socket 48-pin 8GBit NAND Flash inserted U60 NOR Flash socket Socket 56-pin 1GB NOR Flash inserted Figure 5.
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Jumper Default Settings 8 Jumper Default Settings Table 7 lists factory default jumper settings for P5040 DS (SuperHYDRA). Figure 6 notes jumper locations. Table 7. P5040 DS (SuperHYDRA) Jumper Default Settings Jumper Type J11 Header Features 1x3-pin Name/Function Description SD/eMMC card detect selection • 1-2: [Default] eSDHC mode • 2-3: eMMC mode Combined Headers 1x3-pin & 1x1-pin CVDD selection • 1-2: [Default] 3.3V • 2-3: 1.8V • 2-4: 2.
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Push Buttons 9 Push Buttons Table 8 lists the functioning of P5040 DS (SuperHYDRA) push buttons. Figure 7 notes push button Table 8. P5040 DS (SuperHYDRA) Push Buttons Push Button Function Description SW14 Power (ON/OFF) • Press SW14 to assert Power-ON/OFF. • Powered by an external ATX power supply via J43 and J41 power connectors. • System automatically powers-on after asserting ATX power supply if SW9.5=’1’. SW15 Event • Press SW15 to issue processor IRQ4.
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LED Lights 10 LED Lights Figure 8, below, lists the functioning of SuperHYDRA LED lights. See Table 9 for LED locations. Table 9.
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LED Lights Table 9.
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LED Lights Table 9. P5040 DS (SuperHYDRA) LEDs LED D38 Color Name LED ON Green/ Red PS_PL_PROG_ CNTR • Green: Voltage set by SW13 • Red: Voltage set by I2C1 bus LED OFF • OFF: Power OFF Figure 8. P5040 DS (SuperHYDRA) LED (D) Locations P5040 DS Hardware Getting Started, Rev. 1.
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Working Environment 11 Working Environment Features of the working environment are outlined in Table 10. Table 10. P5040 DS (SuperHYDRA) Working Environment Mode Inside PC Box Standalone Components Optional Expansion • ATX12V • 250 GB hard disk • DVD R/W drive • Plug SGMII riser card into PEX slots 1, 2, 3, 5, or 6. • Plug XAUI riser card into PEX slots 1 or 2. • ATX12V • Plug SGMII riser card into PEX slots 1, 2, 3, 5, or 6. • Plug XAUI riser card into PEX slots 1 or 2.
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HW Getting Started Procedures 12.1 Standalone Mode Table 11. Getting Started Procedure: Standalone Mode Getting Started Procedure: Standalone Step 1: Check HW kit contents. Section 4, "Hardware Kit Contents" Step 2: Check default SW settings. Section 6, "Switch Default Settings" Step 3: Check default connector settings. Section 7, "Connector Default Settings" Step 4: Check default jumper settings. Section 8, "Jumper Default Settings" Step 5: Establish working environment.
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HW Getting Started Procedures Table 11. Getting Started Procedure: Standalone Mode Getting Started Procedure: Standalone Step 8: Connect CW USB TAP. CAUTION! Avoid damage, follow the below steps. 1. Align the red stripe of the USB-UTAP connector cable with Pin 1 of the JTAG/COP 16-pin connector (at J39). 4 2. Connect the connector cable to J39. 3. Press SW14 to Power-ON. 4. Check for completion of the reset sequence (D3:30).
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HW Getting Started Procedures 12.2 PC Mid-Tower Mode Table 12 outlines activation steps for a PC Mid-Tower unit. Table 12. Getting Started Procedure: PC Mid-Tower Mode Getting Started Procedure: PC Mid-Tower Step 1: Attach country-specific wall outlet plug to the primary power cable. Step 2: Connect power cable to back of Mid-Tower unit. Step 7 Step 2 Step 3: Connect RS-232 cable to DB9 Cross Gender at J5-Bottom. Step 6 Step 4a: Connect cross-over cable between P1–GETH2 and J2-Top–GETH1.
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HW Getting Started Procedures Table 12. Getting Started Procedure: PC Mid-Tower Mode Getting Started Procedure: PC Mid-Tower Step 8: Power-ON: press the uppermost push button on the front panel of the Mid-Tower PC box. The lighted blue LED encircling the push button indicates power. NOTE! Plugs and USB ports located on the front panel of the Mid-Tower are not functional. Non-functional Step 9: Power-OFF by pressing the same uppermost push button. Blue LED will shut off.
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SerDes Options 13 SerDes Options There are three SerDes module set-up options: SGMII and XAUI riser cards, and PEX loopback cards. Table 13. SerDes Module Set-ups SGMII Riser Card 1. Select a configuration scenario; e.g., switch settings. 2. Connect the supplied cables as instructed in Section 12.1, "Standalone Mode". 3. Insert a SGMII riser card into slots J21, J22 and J24 for P5040 device or alternatively J20 and J21 for P3041/P5020 devices. SGMII Riser Cards 4. Press SW14 to Power-ON.
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SerDes Options P5040 DS Hardware Getting Started, Rev. 1.
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.