Datasheet

3.3.3 Logic analyzer findings
Using a logic analyzer such as the Saleae Logic16 [15] hooked up to GND and the MOSI,
MISO, CLK and SS lines between the console and the original Davis data logger re-
veals which communication is going on there.
The data logger authentication only takes place during the console boot sequence,
either when first powering up the console or after a console reset.
The console starts out by reading the chip status. If the chip status is found accept-
able, the entire 128-byte security register is read and verified.
Figure 7: Capturing the SPI communication between the console and the original Davis data logger.
Here the console issues the 0x77 opcode, followed by three required dummy bytes. The AT45DB011
DataFlash chip then replies with the 128 byte values stored in the security register, here starting with
0x9A 0x2F ...
Recommended configuration settings for the Saleae Logic16 logic analyser:
• Four channels enabled: MOSI, MISO, CLK and CS/SS.
• Sample rate of 50 MHz (25 MHz also used with success).
• MSB first.
• 8 bits per transfer.
• Clock high when inactive (CPOL = 1).
• Data valid on clock trailing edge (CPHA = 1).
• Enable line active when low.
Connect the MISO, MOSI, CLK, CS/SS and GND probes to the respective signal
sources — figure 8 refers.
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