Specifications
DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
Final 43
DM6580 Functional Description
In this chip, we could roughly divide it into two major
parts: digital portion and analog portion. The
functional blocks are described separately in this
section. The analog circuits include a sigma-delta
modulator/demodulator, decimation/interpolation
filters, a speaker driver, low-pass filter and certain
logic circuits. The digital circuits is composed of
Tx/Rx clock generator/PLL, serial port, serial/parallel
conversions and control registers. All the clock
information the analog circuits need should be
provided by the digital clock system since the best
sampling instant of A/D and D/A depends on the
received signal and transmit signals. The data format
of A/D and D/A is 2's complement.
The master clock (FQ) is obtained from an external
signal connected to CLKIN. The different transmit
and receive clocks are obtained by master clock
frequency division in several programmable counters.
The Tx and Rx clocks can be synchronized on
external signals by performing the phase shifts in the
frequency division process. Two independent digital
phase locked loops are implemented using this
principle, one for transmit clock system, the other,
receive clock. The tracking of the transmit clock is
automatically done by the transmit DPLL circuit. The
receive DPLL circuit is controlled by the host
processor and it is actually an adjustable phase
shifter.
DM6580 Register Description
Register D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Programme
dFunctions
TxCR0
R1 X3 X2 X1 X0 N3 N2 N1 N0 R0 S T Tx Data Rate
Clock
TxCR1
Q1 D M1 M0 Q0 F Y U2 U1 U0 Tx Baud
sample Clock
TxCR2
Vol1 Vol2 F1 F0 W ATT LTX LC SST EMX VF Miscellaneou
s control
TxTest
Reserved
RxCR0
R1 H2 H1 H0 N3 N2 N1 N0 R0 S T Rx Data Rate
Clock
RxCR1
Q1 RST D M1 M0 Q0 P Y U2 U1 U0 Rx Baud
SampleClock
RxCR2
-6dB LL PS4 PS3 PS2 PS1 PS0 AP2 AP1 AP0 Rx Phase
Shift Control
RxTest
Reserved
Version: DM562P-DS-F01
February 02, 2004