Datasheet

DTM67207B
2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM
Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 8
SERIAL PRESENCE DETECT MATRIX
Byte# Function Value Hex
0 Number of Bytes Utilized by Module Manufacturer 128 bytes 80
1 Total number of Bytes in SPD device 256 bytes 08
2 Memory Type DDR2 SDRAM 08
3 Number of Row Addresses 14 0E
4 Number of Column Addresses 10 0A
Module Attributes - Number of Ranks, Package and Height 61
Number of Ranks - 2
Card on Card - No
DRAM Package - Planar
5
Module Height - 30mm
6 Module Data Width 64 40
7 Reserved UNUSED 00
8 Voltage Interface Level of this assembly SSTL/1.8V 05
9 SDRAM Cycle time. (Max. Supported CAS Latency). CL=X (ns) 3.75 3D
10 SDRAM Access from Clock. (Highest CAS latency). (t
AC
) (ns) 0.5 50
DIMM configuration type (Non-parity, Parity or ECC) 00
Data Parity -
Data ECC -
Address/Command Parity -
TBD -
TBD -
TBD -
TBD -
11
TBD -
12 Refresh Rate/Type (μs) 7.8 (SR) 82
13 Primary SDRAM Width 8 08
14 Error Checking SDRAM Width None 00
15 Reserved UNUSED 00
SDRAM Device Attributes: Burst Lengths Supported 0C
TBD -
TBD -
Burst Length = 4 - X
Burst Length = 8 - X
TBD -
TBD -
TBD -
16
TBD -
17 SDRAM Device Attributes - Number of Banks on SDRAM Device 8 08