Datasheet
DTM67207B
2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM
Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 6
I
DD
Specifications and Conditions (T
A
= 0 to 70 C, Voltage referenced to V
ss
= 0 V)
PARAMETER Symbol Test Condition
Max
Value
Unit
Operating One
Bank Active-
Precharge Current
I
DD
0
t
CK
= t
CK
(I
DD
), t
RC
= t
RC
(I
DD
), t
RAS
= t
RAS
MIN(I
DD
); CKE is HIGH, /S is
HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching.
920 mA
Operating One
Bank Active-Read-
Precharge Current
I
DD
1
I
OUT
= 0 mA; BL = 4, CL = CL(I
DD
), AL = 0; t
CK
= t
CK
(I
DD
), t
RC
=
t
RC
(I
DD
), t
RAS
= t
RAS
MIN(I
DD
), t
RCD
= t
RCD
(I
DD
); CKE is HIGH, /S is
HIGH between valid commands; Address bus inputs are switch-
ing.
1120 mA
Precharge Power-
Down Current
I
DD
2P
All banks idle; t
CK
= t
CK
(I
DD
); CKE is LOW; Other control and ad-
dress bus inputs are stable; Data bus inputs are floating.
110 mA
Precharge Standby
Current
I
DD
2N
All banks idle; t
CK
= t
CK
(I
DD
); CKE is HIGH, /S is HIGH; Other con-
trol and address bus inputs are switching; Data bus inputs are
switching.
640 mA
Active Power-Down
Current
I
DD
3P
All banks open; t
CK
= t
CK
(I
DD
); CKE is LOW; Other control and ad-
dress bus inputs are stable; Data bus inputs are floating; Fast
Power-down exit (Mode Register bit 12 = 0).
480 mA
Active Standby
Current
I
DD
3N
All banks open; t
CK
= t
CK
(I
DD
), t
RAS
= t
RAS
MAX(I
DD
), t
RP
= t
RP
(I
DD
);
CKE is HIGH, /S is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus inputs are switch-
ing.
720 mA
Operating Burst
Write Current
I
DD
4W
All banks open, continuous burst writes; BL = 4, CL = CL(I
DD
), AL
= 0; t
CK
= t
CK
(I
DD
), t
RAS
= t
RAS
MAX(I
DD
), t
RP
= t
RP
(I
DD
); CKE is HIGH,
/S is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching.
1360 mA
Operating Burst
Read Current
I
DD
4R
All banks open, continuous burst reads, I
OUT
= 0mA; BL = 4, CL =
CL(I
DD
), AL = 0; t
CK
= t
CK
(I
DD
), t
RAS
= t
RAS
MAX(I
DD
), t
RP
= t
RP
(I
DD
);
CKE is HIGH, /S is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching.
1360 mA
Burst Refresh Cur-
rent
I
DD
5
t
CK
= t
CK
(I
DD
); refresh command at every t
RFC
(I
DD
) interval; CKE is
HIGH, /S is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
2040 mA
Self Refresh Cur-
rent
I
DD
6
CK and /CK at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating.
110 mA
Operating Bank In-
terleave Read Cur-
rent
I
DD
7
All bank interleaving reads, I
OUT
= 0 mA; BL = 4, CL = CL(I
DD
), AL
= t
RCD
(I
DD
) - 1 x t
CK
(I
DD
); t
CK
= t
CK
(I
DD
), t
RC
= t
RC
(I
DD
), t
RRD
=
t
RRD
(I
DD
), t
RCD
= t
RCD
(I
DD
); CKE is HIGH, /S is HIGH between valid
commands; Address bus inputs are stable during deselects; Data
bus inputs are switching.
2520 mA
Notes:
1. All currents are based on DRAM absolute maximum values.
2. Unless otherwise specified, for all I
DD
X measurements:
CL(I
DD
) = 4 t
CK
t
CK
(I
DD
) = 3.75 ns
t
RAS
MAX(I
DD
) = 70,000 ns
t
RAS
MIN(I
DD
) = 45 ns
t
RC
(I
DD
) = 60 ns
t
RCD
(I
DD
) = 15 ns
t
RFC
(I
DD
) = 127.5 ns
t
RP
(I
DD
) = 15 ns
t
RRD
(I
DD
) = 7.5 ns