Datasheet

DTM67207B
2 GB – 200-Pin Unbuffered non-ECC DDR2 SO-DIMM
Document 06553, Revision A, 08-Jul-09, Dataram Corporation © 2009 Page 10
31 Module Rank Density 1GB 01
32 Address and Command Setup Time Before Clock (t
IS
) (ns) 0.25 25
33
Address and Command Hold Time After Clock (t
IH
) (ns) 0.37 37
34
Data Input Setup Time Before Strobe (t
DS
) (ns) 0.1 10
35
Data Input Hold Time After Strobe (t
DH
) (ns) 0.22 22
36
Write Recovery Time (t
WR
) (ns) 15 3C
37
Internal write to read command delay (t
WTR
) (ns) 7.5 1E
38
Internal read to precharge command delay (t
RTP
) (ns) 7.5 1E
39
Memory Analysis Probe Characteristics. UNUSED 00
Extension of Byte 41(t
RC
) and Byte 42 (t
RFC
) (ns) 06
Add this value to byte 41 - 0
40
Add this value to byte 42 - 0.5
41
SDRAM Device Minimum Active to Active/Auto Refresh Time (t
RC
) (ns) 60 3C
42
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh
Command Period (t
RFC
). (ns)
127.5 7F
43 SDRAM Device Maximum Cycle Time (t
CK
max). (ns) 8 80
44 SDRAM Dev DQS-DQ Skew for DQS & DQ signals (t
DQSQ
) (ns) 0.3 1E
45 DDR SDRAM Device Read Data Hold Skew Factor (t
QHS
) (ns) 0.4 28
46 PLL Relock Time (μs) UNUSED 00
DRAM maximun Case Temperature Delta. (C) 00
DT4R4W Delta (Bits 0:3) - 0
47
Tcasemax delta (Bits 7:4) - 0
48
Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-
A
DRAM). (C/Watt)
UNUSED 4E
DRAM Case Temperature Rise from Ambient due to Activate-Precharge/
Mode Bits (DT0/Mode Bits). (C)
20
Bit 0: If "0" DRAM does not support high temperature self-refresh entry - 0
Bit 1: If "0" Do not need double refresh rate for the proper operation - 0
49
DT0: (Bits 2:7) - 0
50
DRAM Case Temperature Rise from Ambient due to Precharge/Quiet
Standby (DT2N/DT2Q). (C)
UNUSED 1E
51
DRAM Case Temperature Rise from Ambient due to Precharge Power-Down
(DT2P). (C)
UNUSED 23
52
DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N).
(C)
UNUSED 16
53
DRAM Case temperature Rise from Ambient due to Active Power-Down with
Fast PDN Exit (DT3Pfast). (C)
UNUSED 2C