Datasheet

DTM65523C

4 GB, 240-Pin DDR2 FB-DIMM

NOTES FOR TRANSMITTER OUTPUT SPECIFICATIONS:

1. Specified at the package pins into a timing and voltage compliance test load. Common-mode measurements are

performed using a 101010 pattern.

2. This is the ratio of the V

TX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit

after a transition.

3. De-emphasis is disabled in the calibration state.

4. Includes all sources of AC common mode noise

5. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as the Electrical

Idle condition.

6. Specified at the package pins into a voltage compliance test load. Transmitters meet both single-ended and differential

output E1 specifications.

7. This specification, considered with V

RX-IDLE-SE-DC, implies a maximum 15mV single-ended DC offset between Tx and Rx

pins during the electrical idle condition. This in turn allows a ground offset between adjacent FB-DIMM agents of 26mV

when worst-case termination resistance matching is considered.

8. The maximum value is specified to be at least (V

TX-DIFFp-p L / 4) + VTX-CM L + (VTX-CM-ACp-p / 2)

9. This number does not include the effects of SSC or reference clock jitter.

10. These timing specifications apply to resync mode only.

11. Defined as the dual-dirac deterministic jitter as described in Section 4 of the JEDEC FB-DIMM High Speed Differential

PTP Link Draft Spec rev 0.8.

12. Pulse width measured at 0V differential.

13. The termination small signal resistance; tolerance across voltages from 100mV to 400mV shall not exceed ±5: with regard

to the average of the values measured at 100mV and at 400mV for that pin.

14. Lane to Lane skew at the Transmitter pins for an end component.

15. Lane to Lane skew at the Transmitter pins for an intermediate component (assuming zero Lane to Lane skew at the

Receiver pins of the incoming PORT).

16. This is a static skew. A FB-DIMM component is not allowed to change its lane to lane phase relationship after

initialization.

17. Measured from the reference clock edge to the center of the output eye. This specification is met across specified voltage

and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of the

receiver.

18. BER per differential lane.